mxc_setup_mxc91331.h

i.mx31 3DS平台Nandboot引导程序源码

#define         EUartUSR2_BRCD      (1 << 2)    // Break condition
#define         EUartUSR2_ORE       (1 << 1)    // Overrun error
#define         EUartUSR2_RDR       (1 << 0)    // Recv data ready
#define         EUartUTS_FRCPERR    (1 << 13)   // Force parity error
#define         EUartUTS_LOOP       (1 << 12)   // Loop tx and rx
#define         EUartUTS_TXEMPTY    (1 << 6)    // TxFIFO empty
#define         EUartUTS_RXEMPTY    (1 << 5)    // RxFIFO empty
#define         EUartUTS_TXFULL     (1 << 4)    // TxFIFO full
#define         EUartUTS_RXFULL     (1 << 3)    // RxFIFO full
#define         EUartUTS_SOFTRST    (1 << 0)    // Software reset

#define         DelayTimerPresVal   3

#define         L2CC_ENABLED

/* Assuming 26MHz input clock */
/*                         PD          MFD           MFI          MFN */
#define         MPCTL_PARAM_208  ((1 << 26) + (0   << 16) + (8  << 11) + (0  << 0))
#define         MPCTL_PARAM_399  ((0 << 26) + (51  << 16) + (7  << 11) + (35 << 0))
#define         MPCTL_PARAM_532  ((0 << 26) + (51  << 16) + (10 << 11) + (12 << 0))
      
/* Definitions from mxc91331/evb/current/include/mxc91331.h */
#define         PBC_BASE                        CS4_BASE_ADDR    /* Peripheral Bus Controller */
#define         MXC91331EVB_CS_LAN_BASE        (CS4_BASE_ADDR + 0x00020000 + 0x300)
#define         MXC91331EVB_CS_UART_BASE       (CS4_BASE_ADDR + 0x00010000)

#define         REDBOOT_IMAGE_SIZE              0x40000

#define         SDRAM_WORKAROUND_FULL_PAGE

//#define       ARMHIPG_208_52_52         /* ARM: 208MHz, HCLK=IPG=52MHz*/
//#define       ARMHIPG_52_52_52          /* ARM: 52MHz, HCLK=IPG=52MHz*/
//#define       ARMHIPG_399_66_66
#define         ARMHIPG_399_133_66

/* MXC91331 EVB SDRAM is from 0x80000000, 64M */
#define         SDRAM_BASE_ADDR                 CSD0_BASE_ADDR
#define         SDRAM_SIZE                      0x04000000

#define         UART_WIDTH_32         /* internal UART is 32bit access only */
#define         EXT_UART_x16

#define         UART_WIDTH_32         /* internal UART is 32bit access only */


#define         FLASH_BURST_MODE_ENABLE 1
#define         SDRAM_COMPARE_CONST1    0x55555555
#define         SDRAM_COMPARE_CONST2    0xAAAAAAAA
#define         UART_FIFO_CTRL          0x881
#define         TIMEOUT                 1000

/* moved from uart.c file */

#define SETUP_IOMUX()                                         \
{                                                                 \
        volatile unsigned int *pMuxCtl;                           \
        pMuxCtl = (volatile unsigned int *)(IOMUXC_BASE_ADDR);                \
        pMuxCtl[83] = (pMuxCtl[83] & 0xFF0FFF0F) | 0x00380024;    \
        pMuxCtl[84] = (pMuxCtl[84] & 0xFFFF0FFF) | 0x00003000;    \
}
                        

#if defined(__ASSEMBLER__) //ADDED FOR COMPILATION

/* 
 * Platform setup macro
 */
#define PLATFORM_SETUP1 _platform_setup1

/* This macro represents the initial startup code for the platform */
    .macro  _platform_setup1
MXC91331_SETUP_START:
        /* Make sure LE */
        mrc 15, 0, r0, c1, c0, 0
        bic r0, r0, #0x80
        mcr 15, 0, r0, c1, c0, 0
        /*
         * - set correct memory timings & bus widths
         * - configure chip select lines
         * - init anything that could be undefined after reset
         */
        /*
         * Step 1: ARM1136 init 
         *       - invalidate I/D cache/TLB and drain write buffer; 
         *       - invalidate L2 cache
         *       - unaligned access
         *       - branch predictions
         */
#ifdef TURN_OFF_IMPRECISE_ABORT
        mrs    r0, cpsr
        bic    r0, r0, #0x100
        msr    cpsr, r0
#endif

        mov r0, #0
        mcr 15, 0, r0, c7, c7, 0        /* invalidate I cache and D cache */
        mcr 15, 0, r0, c8, c7, 0        /* invalidate TLBs */
        mcr 15, 0, r0, c7, c10, 4        /* Drain the write buffer */

        /* Also setup the Peripheral Port Remap register inside the core */
        ldr r0, =0x40000015        /* start from AIPS 2GB region */
        mcr p15, 0, r0, c15, c2, 4
        
        /*** L2 Cache setup/invalidation/disable ***/
        /* Disable L2 cache first */
        ldr r0, =L2CC_BASE_ADDR
        ldr r2, [r0, #L2_CACHE_CTL_REG]
        bic r2, r2, #0x1
        str r2, [r0, #L2_CACHE_CTL_REG]
        /*
         * Configure L2 Cache:
         * - 128k size(16k way)
         * - 8-way associativity
         * - 0 ws TAG/VALID/DIRTY
         * - 4 ws DATA R/W
         */
        ldr r1, [r0, #L2_CACHE_AUX_CTL_REG]
        and r1, r1, #0xFE000000
        ldr r2, =0x00030024
        orr r1, r1, r2
        str r1, [r0, #L2_CACHE_AUX_CTL_REG]

        /* Invalidate L2 */
        ldr r1, =0x000000FF
        str r1, [r0, #L2_CACHE_INV_WAY_REG]
L2_loop:
        /* Poll Invalidate By Way register */
        ldr r2, [r0, #L2_CACHE_INV_WAY_REG]
        cmp r2, #0
        bne L2_loop

        /*** End of L2 operations ***/

/*
 * End of Step 1: ARM1136 init
 */

        /*
         * Step 2: AIPI setup 
         *        Only setup MPROTx registers. The PACR default values are good.
         */
        /* 
         * Set all MPROTx to be non-bufferable, trusted for R/W, 
         * not forced to user-mode.
         */
        ldr r0, =AIPS1_CTRL_BASE_ADDR
        ldr r1, =0x77777777
        str r1, [r0, #0x00]                
        str r1, [r0, #0x04]
        ldr r0, =AIPS2_CTRL_BASE_ADDR
        str r1, [r0, #0x00]
        str r1, [r0, #0x04]

        /*
         * Clear the on and off peripheral modules Supervisor Protect bit
         * for SDMA to access them. Did not change the AIPS control registers
         * (offset 0x20) access type
         */
        ldr r0, =AIPS1_CTRL_BASE_ADDR
        ldr r1, =0x0
        str r1, [r0, #0x40]
        str r1, [r0, #0x44]
        str r1, [r0, #0x48]
        str r1, [r0, #0x4C]
        ldr r1, [r0, #0x50]
        and r1, r1, #0x00FFFFFF
        str r1, [r0, #0x50]

        ldr r0, =AIPS2_CTRL_BASE_ADDR
        ldr r1, =0x0
        str r1, [r0, #0x40]
        str r1, [r0, #0x44]
        str r1, [r0, #0x48]
        str r1, [r0, #0x4C]
        ldr r1, [r0, #0x50]
        and r1, r1, #0x00FFFFFF
        str r1, [r0, #0x50]
        /*
         * End of Step 2: AIPI setup
         */

        /* 
         * Step 3: MAX (Multi-Layer AHB Crossbar Switch) setup
         */
        ldr r0, =MAX_BASE_ADDR
        /* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */
        ldr r1, =0x00302154                
        str r1, [r0, #0x000]        /* for S0 */
        str r1, [r0, #0x100]        /* for S1 */
        str r1, [r0, #0x200]        /* for S2 */
        str r1, [r0, #0x300]        /* for S3 */
        str r1, [r0, #0x400]        /* for S4 */
        /* SGPCR - always park on last master */
        ldr r1, =0x10                        
        str r1, [r0, #0x010]        /* for S0 */
        str r1, [r0, #0x110]        /* for S1 */
        str r1, [r0, #0x210]        /* for S2 */
        str r1, [r0, #0x310]        /* for S3 */
        str r1, [r0, #0x410]        /* for S4 */
        /* MGPCR - restore default values */
        ldr r1, =0x0
        str r1, [r0, #0x800]        /* for M0 */
        str r1, [r0, #0x900]        /* for M1 */
        str r1, [r0, #0xA00]        /* for M2 */
        str r1, [r0, #0xB00]        /* for M3 */
        str r1, [r0, #0xC00]        /* for M4 */
        str r1, [r0, #0xD00]        /* for M5 */
        /*
         * End of Step 3: MAX setup
         */

        /*
 * Step 4: setup SPBA to allow all 3 masters to have access to these shared peripherals
         */
        ldr r0, =SPBA_CTRL_BASE_ADDR
        add r4, r0, #0x38
        ldr r1, =0x7            /* allow all 3 masters access */
        ldr r2, =0xC0010007
spba_continue:
        str r1, [r0]
spba_check_loop:
        ldr r3, [r0]
        cmp r2, r3
        bne spba_check_loop
        add r0, r0, #4
        cmp r0, r4
        ble spba_continue

        /*
         * End of Step 4: SPBA setup
         */

        /*
 * Step 5: Signal drive strength setup
 */
        ldr r0,=(IOMUXC_BASE_ADDR + 0x300)

        /* Set max drive strength for SDRAM address lines */
        mov r1, #0x00700000 
        str r1, [r0, #0x11C]

        /* Set max drive strength for SDRAM SD0-SD15 data lines */
        mov r1, #0x00700000 
        str r1, [r0, #0xF8]

        /* Set max drive strength for SDRAM SD16-SD31 data lines */
        mov r1, #0x00001C00 
        str r1, [r0, #0xE4]

        /* Set max drive strength for SDRAM DQMx lines */
        ldr r1, =0x00701004
        str r1, [r0, #0xC8]

        /* Set max drive strength for OE line */
        ldr r1, =0x00401800
        str r1, [r0, #0xC4]

        /* Set max drive strength for Dx lines */
        mov r1, #0x00001800
        str r1, [r0, #0xA0]

        /* Set max drive strength for SDRAM SDQS lines */
        mov r1, #0x00000007
        str r1, [r0, #0xD0]
/*
 * End of Step 5: drive strength setup
 */


/*
 * Step 6: Clock setup
 *        - These are the targeted speed settings (may not be true for now).
         * Note: the default USBPLL seems to be 286MHz instead of 288MHz?

           Module           Freq (MHz)   Note
           =========================================================================
           ARM core         399          ipg_clk_arm
           AHB              133          known as "hclk", ipg_clk_max
           IP               66.5         ipg_clk (also used as ipg_per_clk ???)
           EMI              133          =hclk
         */
        ldr r0, =CRM_MCU_BASE_ADDR
        ldr r1, =0x18FF2900
        str r1, [r0, #CLKCTL_MCR]
upll_lock:
        ldr r1, [r0, #CLKCTL_MCR]
        ands r1, r1, #0x80
        beq upll_lock

        /*
         * J10 (CPU card) - CKO1=MCU_PLL div by 16
         * J9 (CPU card) - CKO2=MCU_AHB div by 16
         */
        ldr r1, =0x27060
        str r1, [r0, #CLKCTL_COSR]

        /* If SDRAM has been setup, bypass clock/WEIM setup */
        ldr r3, =ESDCTL_BASE
        ldr r1, [r3]
        ands r1, r1, #0x80000000
        bne HWInitialise_skip_SDRAM_setup

#ifdef ARMHIPG_208_52_52
        ldr r1, =0xFF800518          /* ARM=208MHz, HCLK=52MHz, IPG=52MHz */
        str r1, [r0, #CLKCTL_PDR0]
        ldr r1, =MPCTL_PARAM_208
        str r1, [r0, #CLKCTL_MPCTL]
#endif