📄 sa11x1.h
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//
// Copyright (c) Microsoft Corporation. All rights reserved.
//
//
// Use of this source code is subject to the terms of the Microsoft end-user
// license agreement (EULA) under which you licensed this SOFTWARE PRODUCT.
// If you did not accept the terms of the EULA, you are not authorized to use
// this source code. For a copy of the EULA, please see the LICENSE.RTF on your
// install media.
//
/* SA11x1 defines */
#ifndef __SA11x1_H__
#define __SA11x1_H__
/* get board specific base addresses */
//#include "SA11X1DB.h"
#ifdef USING_SA1101
#define FillSize 255
#include "SA1101.h"
#else
#define FillSize 0
#endif
/* System Controller (SBI) */
#ifdef USING_SA1101
struct skpcrBITS {
unsigned UCLKEn : 1;
unsigned PCLKEn : 1;
unsigned ICLKEn : 1;
unsigned VCLKEn : 1;
unsigned IEEECLKEn : 1;
unsigned DCLKEn : 1;
unsigned nKPADEn : 1;
unsigned rsvd0 :25;
};
struct skcdrBITS {
unsigned PllMul : 7;
unsigned VCLKDiv : 2;
unsigned BCLKDiv : 1;
unsigned UTestCLKEn : 1;
unsigned DivRValue : 6;
unsigned DivNValue : 5;
unsigned PLLRSH : 3;
unsigned PFD_CP13 : 1;
unsigned ClkOutTestMode : 1;
unsigned TClkGen : 1;
unsigned VideoJitterComp : 3;
unsigned rsvd0 : 1;
};
struct skdacdrBITS {
unsigned DACCount : 8;
unsigned rsvd0 :24;
};
struct SK_SC_PLLRegisterBlock {
unsigned rsvd0 [1+FillSize];
struct skpcrBITS skpcr [1+FillSize];
unsigned rsvd1[256-2] [1+FillSize];
struct skcdrBITS skcdr [1+FillSize];
unsigned rsvd2[128-1] [1+FillSize];
struct skdacdrBITS dacdr1 [1+FillSize];
struct skdacdrBITS dacdr2 [1+FillSize];
};
#define SK_PLL_BASE 0
#else
struct skpcrBITS {
unsigned UCLKEn : 1;
unsigned ACCLKEn : 1;
unsigned I2SCLKEn : 1;
unsigned L3CLKEn : 1;
unsigned SCLKEn : 1;
unsigned PMCLKEn : 1;
unsigned PTCLKEn : 1;
unsigned DCLKEn : 1;
unsigned PWMCLKEn : 1;
unsigned rsvd0 :23;
};
struct skcdrBITS {
unsigned FBDiv : 7;
unsigned IPDiv : 5;
unsigned OPDiv : 2;
unsigned OPSel : 1;
unsigned RCLKDiv : 2;
unsigned UTESTClkEn : 1;
unsigned CLKTestMode : 1;
unsigned CLKTestEn : 1;
unsigned rsvd0 :12;
};
struct skaudBITS {
unsigned ACDiv : 7;
unsigned rsvd0 :25;
};
struct skpmcBITS {
unsigned PMCDiv : 7;
unsigned rsvd0 :25;
};
struct skptcBITS {
unsigned PTCDiv : 7;
unsigned rsvd0 :25;
};
struct skpenBITS {
unsigned PWMen : 1;
unsigned rsvd0 :31;
};
struct skpwmBITS {
unsigned PWMCK : 8;
unsigned rsvd0 :24;
};
struct skdacdrBITS {
unsigned DACCount : 8;
unsigned rsvd0 :24;
};
struct SK_SC_PLLRegisterBlock {
struct skpcrBITS skpcr [1+FillSize];
struct skcdrBITS skcdr [1+FillSize];
struct skaudBITS skaud [1+FillSize];
struct skpmcBITS skpmc [1+FillSize];
struct skptcBITS skptc [1+FillSize];
struct skpenBITS skpen0 [1+FillSize];
struct skpwmBITS skpwm0 [1+FillSize];
struct skpenBITS skpen1 [1+FillSize];
struct skpwmBITS skpwm1 [1+FillSize];
};
#define SK_PLL_BASE (0x200)
#define SK_SC_PLL_BA (SK_BA + SK_PLL_BASE)
#define SK_SC_PLL_SPACE (sizeof(struct SK_SC_PLLRegisterBlock))
#endif
#ifdef USING_SA1101
struct skcrBITS {
unsigned PLLen : 1;
unsigned BCLKEn : 1;
unsigned Sleep : 1;
unsigned IRefEn : 1;
unsigned VCOON : 1;
unsigned ScanTestEn : 1;
unsigned ClockTestEn : 1;
unsigned rsvd0 :25;
};
/* System Bus Interface (SBI) */
struct smcrBITS {
unsigned dcac : 2;
unsigned drac : 2;
unsigned arbBias : 1;
unsigned vmarAddrTop : 4;
unsigned rsvd0 :23;
};
struct snprBITS {
unsigned VFBstart :12;
unsigned VFBsize :11;
unsigned ignoreBits : 1;
unsigned colSel : 3;
unsigned bankSel : 2;
unsigned rsvd0 : 2;
unsigned enSnoop : 1;
};
struct SK_SMCRegisterBlock{
// struct skcrBITS skcr[1+FillSize];
// unsigned rsvd0[0x500-1][1+FillSize];
struct smcrBITS smcr[1+FillSize];
struct snprBITS snpr[1+FillSize];
};
#define SMC_BASE (0x0140000)
#define SK_SMC_BA (SK_BA + SMC_BASE)
#else
/* System Bus Interface (SBI) */
struct skcrBITS {
unsigned PLL_Bypass : 1;
unsigned RCLKEn : 1;
unsigned Sleep : 1;
unsigned Doze : 1;
unsigned VCO_OFF : 1;
unsigned ScanTestEn : 1;
unsigned ClockTestEn : 1;
unsigned RdyEn : 1;
unsigned SeLAC : 1;
unsigned OPPC : 1;
unsigned PllTestEn : 1;
unsigned UsbIOTestEn : 1;
unsigned rsvd0 :1;
unsigned nOE_EN : 1;
unsigned rsvd1 :18;
};
struct smcrBITS {
unsigned dtim : 1;
unsigned mbge : 1;
unsigned drac : 3;
unsigned clat : 1;
unsigned rsvd0 :26;
};
struct SK_SMCRegisterBlock {
struct skcrBITS skcr[1+FillSize];
struct smcrBITS smcr[1+FillSize];
unsigned skID[1+FillSize];
};
#define SMC_BASE (0x0000000)
#define SK_SMC_BA (SK_BA + SMC_BASE)
#endif
#define SK_KCR_BA (SK_BA)
#define SK_SMC_SPACE (sizeof(struct SK_SMCRegisterBlock))
struct statusBITS {
unsigned rsvd0 : 7;
unsigned irqHciRmtWkp : 1;
unsigned irqHciBuffAcc : 1;
unsigned nIrqHciM : 1;
unsigned nHciMFCir : 1;
#ifdef USING_SA1101
unsigned rsvd1 :21;
#else
unsigned usbPwrSense : 1;
unsigned rsvd1 :20;
#endif
};
struct resetBITS {
unsigned forceIfReset : 1;
unsigned forceHcReset : 1;
unsigned clkGenReset : 1;
#ifdef USING_SA1101
unsigned rsvd0 :29;
#else
unsigned simScaleDownClk: 1;
unsigned usbintTest : 1;
unsigned uSleepStandbyEn: 1;
unsigned pwrSensePolLow : 1;
unsigned pwrCtrlPolLow : 1;
unsigned rsvd0 :24;
#endif
};
struct irqTestBITS {
unsigned rsvd0 : 7;
unsigned irqHciRmtWkp : 1;
unsigned irqHciBuffAcc : 1;
unsigned nIrqHciM : 1;
unsigned nHciMFCir : 1;
unsigned usbPortResume : 1;
unsigned rsvd1 :20;
};
struct SK_USBRegisterBlock {
unsigned Revision [1+FillSize];
unsigned Control [1+FillSize];
unsigned CommandStatus [1+FillSize];
unsigned InterruptStatus [1+FillSize];
unsigned InterruptEnable [1+FillSize];
unsigned InterruptDisable [1+FillSize];
unsigned HCCA [1+FillSize];
unsigned PeriodCurrentED [1+FillSize];
unsigned ControlHeadED [1+FillSize];
unsigned ControlCurrentED [1+FillSize];
unsigned BulkHeadED [1+FillSize];
unsigned BulkCurrentED [1+FillSize];
unsigned DoneHead [1+FillSize];
unsigned FmInterval [1+FillSize];
unsigned FmRemaining [1+FillSize];
unsigned FmNumber [1+FillSize];
unsigned PeriodicStart [1+FillSize];
unsigned LSThreshold [1+FillSize];
unsigned RhDescriptorA [1+FillSize];
unsigned RhDescriptorB [1+FillSize];
unsigned RhStatus [1+FillSize];
unsigned RhPortStatus [1+FillSize];
unsigned rsvd0[43] [1+FillSize];
unsigned ustar [1+FillSize];
unsigned uswer [1+FillSize];
unsigned usrfr [1+FillSize];
unsigned usnfr [1+FillSize];
unsigned ustcsr [1+FillSize];
struct statusBITS ussr [1+FillSize];
struct resetBITS Reset [1+FillSize];
struct irqTestBITS InterruptTest [1+FillSize];
unsigned rsvd1[3] [1+FillSize];
unsigned ReadDataFifoRAMTestAccess[12][1+FillSize];
};
#ifdef USING_SA1101
#define USB_BASE (0x00180000)
#else
#define USB_BASE (0x00000400)
#endif
#define SK_USB_HCI_BA (SK_BA +USB_BASE)
#define SK_USB_HCI_SPACE (sizeof(struct SK_USBRegisterBlock))
#ifdef USING_SA1111
struct sacr0BITS {
unsigned enb : 1;
unsigned rsvd0 : 1;
unsigned bckd : 1;
unsigned rst : 1;
unsigned ctrl0 : 2; // Must be set to 0
unsigned rsvd1 : 2;
unsigned tfth : 4;
unsigned rfth : 4;
unsigned rsvd2 :16;
};
struct sacr1BITS {
unsigned amsl : 1;
unsigned l3en : 1;
unsigned l3mb : 1;
unsigned drec : 1;
unsigned drpl : 1;
unsigned enlbf : 1;
unsigned rsvd0 :26;
};
struct sacr2BITS {
unsigned ts3v : 1;
unsigned ts4v : 1;
unsigned wkup : 1;
unsigned drec : 1;
unsigned drpl : 1;
unsigned enlbf : 1;
unsigned reset : 1;
unsigned rsvd0 :25;
};
struct sasr0BITS {
unsigned tnf : 1;
unsigned rne : 1;
unsigned bsy : 1;
unsigned tfs : 1;
unsigned rfs : 1;
unsigned tur : 1;
unsigned ror : 1;
unsigned rsvd0 : 1;
unsigned tfl : 4;
unsigned rfl : 4;
unsigned l3wd : 1;
unsigned l3rd : 1;
unsigned rsvd1 :14;
};
struct sasr1BITS {
unsigned tnf : 1;
unsigned rne : 1;
unsigned bsy : 1;
unsigned tfs : 1;
unsigned rfs : 1;
unsigned tur : 1;
unsigned ror : 1;
unsigned rsvd0 : 1;
unsigned tfl : 4;
unsigned rfl : 4;
unsigned cadt : 1;
unsigned sadr : 1;
unsigned rst0 : 1;
unsigned clpm : 1;
unsigned crdy : 1;
unsigned rs3v : 1;
unsigned rs4v : 1;
unsigned rsvd1 : 9;
};
struct sascrBITS {// mach with doc
unsigned rsvd0 : 5;
unsigned tur : 1;
unsigned ror : 1;
unsigned rsvd1 : 9;
unsigned dts : 1;
unsigned rdd : 1;
unsigned sto : 1;
unsigned rsvd2 :13;
};
struct l3carBITS {
unsigned adr : 8;
unsigned rsvd0 :24;
};
struct l3cdrBITS {
unsigned dat : 8;
unsigned rsvd0 : 24;
};
//struct accarBITS { // pkdebug. Orig.
// unsigned dcar :20;
// unsigned rsvd0 :12;
//};
struct accarBITS { // pkdebug. The low order 12 bits are reserved.
unsigned rsvd0 :12;
unsigned dcar :20;
};
//struct accdrBITS { // pkdebug. Orig.
// unsigned cdr :20;
// unsigned rsvd0 :12;
//};
struct accdrBITS { // pkdebug. Low order 4 bits are reserved.
unsigned rsvd0 : 4;
unsigned cdr :16;
unsigned rsvd1 :12;
};
//struct acsarBITS { // pkdebug. Orig
// unsigned sar :20;
// unsigned rsvd0 :12;
//};
struct acsarBITS { // pkdebug. Low order 4 bits are read as zeros.
unsigned rsvd0 : 4;
unsigned sar :16;
unsigned rsvd1 :12;
};
//struct acsdrBITS { // pkdebug. Orig.
// unsigned sdr :20;
// unsigned rsvd0 :12;
//};
struct acsdrBITS { // pkdebug. Low order 4 bits are read as zeros.
unsigned rsvd0 : 4;
unsigned sdr :16;
unsigned rsvd1 :12;
};
struct sadcsBITS {
unsigned den : 1;
unsigned die : 1;
unsigned rsvd0 : 1;
unsigned dbda : 1;
unsigned dsta : 1;
unsigned dbdb : 1;
unsigned dstb : 1;
unsigned biu : 1;
unsigned rsvd1 :24;
};
struct sadcBITS {
unsigned dc :13;
unsigned rsvd0 :19;
};
struct saitrBITS {
unsigned tfs : 1;
unsigned rfs : 1;
unsigned tur : 1;
unsigned ror : 1;
unsigned cadt : 1;
unsigned sadr : 1;
unsigned rsto : 1;
unsigned rsvd0 : 1;
unsigned tdbda : 1;
unsigned tdbdb : 1;
unsigned rdbda : 1;
unsigned rdbdb : 1;
unsigned rsvd1 :20;
};
struct sadrBITS {
unsigned dtl :16;
unsigned dth :16;
};
struct SK_SACRegisterBlock {
struct sacr0BITS sacr0 [1+FillSize];
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