ml675050.h

OKI 675050 hardware accelerator sample program

#define EXIRQSB_IRQ39           0x00000080
#define EXIRQSB_IRQ40           0x00000100
#define EXIRQSB_IRQ41           0x00000200
#define EXIRQSB_IRQ42           0x00000400
#define EXIRQSB_IRQ43           0x00000800
#define EXIRQSB_IRQ44           0x00001000
#define EXIRQSB_IRQ45           0x00002000
#define EXIRQSB_IRQ46           0x00004000
#define EXIRQSB_IRQ47           0x00008000

/* bit field of EXIRQC register */
#define EXIRQC_IRQ48            0x00000001
#define EXIRQC_IRQ49            0x00000002
#define EXIRQC_IRQ50            0x00000004
#define EXIRQC_IRQ51            0x00000008
#define EXIRQC_IRQ52            0x00000010
#define EXIRQC_IRQ53            0x00000020
#define EXIRQC_IRQ54            0x00000040
#define EXIRQC_IRQ55            0x00000080
#define EXIRQC_IRQ56            0x00000100
#define EXIRQC_IRQ57            0x00000200
#define EXIRQC_IRQ58            0x00000400
#define EXIRQC_IRQ59            0x00000800
#define EXIRQC_IRQ60            0x00001000
#define EXIRQC_IRQ61            0x00002000
#define EXIRQC_IRQ62            0x00004000
#define EXIRQC_IRQ63            0x00008000

/* bit field of EXILCC register */
#define EXILCC_ILC48            0x00000007      /* IR48,IR49 */
#define EXILCC_ILC50            0x00000070      /* IR50,IR51 */
#define EXILCC_ILC52            0x00000700      /* IR52,IR53 */
#define EXILCC_ILC54            0x00007000      /* IR54,IR55 */
#define EXILCC_ILC56            0x00070000      /* IR56,IR57 */
#define EXILCC_ILC58            0x00700000      /* IR58,IR59 */
#define EXILCC_ILC60            0x07000000      /* IR60,IR61 */
#define EXILCC_ILC62            0x70000000      /* IR62,IR63 */

/* bit field of EXIRQSC register */
#define EXIRQSC_IRQ48           0x00000001
#define EXIRQSC_IRQ49           0x00000002
#define EXIRQSC_IRQ50           0x00000004
#define EXIRQSC_IRQ51           0x00000008
#define EXIRQSC_IRQ52           0x00000010
#define EXIRQSC_IRQ53           0x00000020
#define EXIRQSC_IRQ54           0x00000040
#define EXIRQSC_IRQ55           0x00000080
#define EXIRQSC_IRQ56           0x00000100
#define EXIRQSC_IRQ57           0x00000200
#define EXIRQSC_IRQ58           0x00000400
#define EXIRQSC_IRQ59           0x00000800
#define EXIRQSC_IRQ60           0x00001000
#define EXIRQSC_IRQ61           0x00002000
#define EXIRQSC_IRQ62           0x00004000
#define EXIRQSC_IRQ63           0x00008000

/* bit field of EXFIQ register */
#define EXFIQ_EXFIQ             0x00000001

/* bit field of EXFIDM register */
#define EXFIDM_FIDM             0x00000001      /* Select interrupt detection mode */


/*****************************************************/
/*    LCD Control Register                           */
/*****************************************************/
#define LCR_BASE        0x7C000000              /* base address of LCD Control Register */
#define LCDCTMG1        (LCR_BASE+0x00)         /* LCD timing register 1 */
#define LCDCTMG2        (LCR_BASE+0x04)         /* LCD timing register 2 */
#define LCDCTMG3        (LCR_BASE+0x08)         /* LCD timing register 3 */
#define LCDCCTRL        (LCR_BASE+0x0C)         /* LCD control register */
#define LCDCSTS         (LCR_BASE+0x10)         /* Status register */
#define LCDCINT         (LCR_BASE+0x14)         /* Interrupt source register */
#define LCDCMASK        (LCR_BASE+0x18)         /* Mask register */
#define LCDCINTCLR      (LCR_BASE+0x1C)         /* Interrupt clear register */

/* bit field of LCDCTMG1 register */
#define LCDCTMG1_ADT            0x000001FF      /* Panel clock count per line */
#define LCDCTMG1_LPW            0x00001E00      /* Line synchronizing pulse width */
#define LCDCTMG1_HFP            0x00FF0000      /* Length between the end of valid data and the start of lcdlp pulse */
#define LCDCTMG1_HBP            0xFF000000      /* Length between the end of line synchronizing pulse and the start of valid data */

/* bit field of LCDCTMG2 register */
#define LCDCTMG2_LPP            0x000001FF      /* Line synchronizing pulse count per valid line */
#define LCDCTMG2_FPW            0x00001E00      /* Frame synchronizing pulse(FLM)width */
#define LCDCTMG2_VFP            0x003F0000      /* Interval between the end of valid line and the start of the FLM */
#define LCDCTMG2_VBP            0x3F000000      /* Interval between the FLM and the start of valid line */

/* bit field of LCDCTMG3 register */
#define LCDCTMG3_RCD            0x0000001F      /* Clock dividing ratio */
#define LCDCTMG3_LCLKON         0x00000020      /* LCDC reference clock */
#define LCDCTMG3_FPPOL          0x00000040      /* FLM polarity */
#define LCDCTMG3_LPPOL          0x00000080      /* LP polarity */
#define LCDCTMG3_CPPOL          0x00000100      /* CPO porarity */
#define LCDCTMG3_DFF            0x00000200      /* DF reverse mode */
#define LCDCTMG3_DF             0x00007C00      /* DF reverse cycle */
#define LCDCTMG3_OEPOL          0x00008000      /* DATAENB polarity */
#define LCDCTMG3_CPBLK          0x00010000      /* CPO level when LCD data unavailable */
#define LCDCTMG3_LPBLK          0x00020000      /* LP level when LCD data unavailable */

/* bit field of LCDCCTRL register */
#define LCDCCTRL_LCDEN          0x00000001      /* Control LCD control signal */
#define LCDCCTRL_DPDMOD         0x00004000      /* LCD data display mode */

/* bit field of LCDCSTS register */
#define LCDCSTS_VBLANK          0x00000001      /* Virtical blank status */
#define LCDCSTS_VSYNC           0x00000002      /* FLM status */
#define LCDCSTS_HBLANK          0x00000004      /* Horizontal blank status */
#define LCDCSTS_HSYNC           0x00000008      /* LP status */

/* bit field of LCDCINT register */
#define LCDCINT_VBNKINT         0x00000001      /* Virtical blank interrupt request */
#define LCDCINT_VSINT           0x00000002      /* FLM interrupt request */

/* bit field of LCDCMASK register */
#define LCDCMASK_VBMASK         0x00000001      /* Virtical blank interrupt mask */
#define LCDCMASK_VSMASK         0x00000002      /* FLM interrupt mask */

/* bit field of LCDCINTCLR register */
#define LCDCINTCLR_VBCLR        0x00000001      /* Clear Virtical blank interrupt request */
#define LCDCINTCLR_VSCLR        0x00000002      /* Clear FLM interrupt request */


/*****************************************************/
/*    ADC Control Register                           */
/*****************************************************/
#define ADC_BASE        0xB6000000              /* base address of ADC Control Register */
#define ADCON0          (ADC_BASE+0x00)         /* A/D control 0 register */
#define ADCON1          (ADC_BASE+0x04)         /* A/D control 1 register */
#define ADCON2          (ADC_BASE+0x08)         /* A/D control 2 register */
#define ADINT           (ADC_BASE+0x0C)         /* A/D interrupt control register */
#define ADFINT          (ADC_BASE+0x10)         /* A/D forced interrupt register */
#define ADR0            (ADC_BASE+0x14)         /* A/D result 0 register */
#define ADR1            (ADC_BASE+0x18)         /* A/D result 1 register */
#define ADR2            (ADC_BASE+0x1C)         /* A/D result 2 register */
#define ADR3            (ADC_BASE+0x20)         /* A/D result 3 register */
#define ADR4            (ADC_BASE+0x24)         /* A/D result 4 register */
#define ADR5            (ADC_BASE+0x28)         /* A/D result 5 register */
#define ADR6            (ADC_BASE+0x2C)         /* A/D result 6 register */
#define ADR7            (ADC_BASE+0x30)         /* A/D result 7 register */

/* bit field of ADCON0 register */
#define ADCON0_ADSNM            0x00000007      /* Scan mode start channel */
#define ADCON0_ADRUN            0x00000010      /* Start A/D conversion */
#define ADCON0_SCNC             0x00000040      /* Loop scan (off/on) */

/* bit field of ADCON1 register */
#define ADCON1_ADSTM            0x00000007      /* A/D conversion channel for select mode */
#define ADCON1_STS              0x00000010      /* A/D conversion start/stop for selection mode */

/* bit field of ADCON2 register */
#define ADCON2_ACKSEL           0x00000003      /* A/D converter clock frequency */

/* bit field of ADINT register */
#define ADINT_INTSN             0x00000001      /* CH7 A/D conversion is completed */
#define ADINT_INTST             0x00000002      /* A/D conversion compleded for select mode */
#define ADINT_ADSNIE            0x00000004      /* Enable interrupt when CH7 A/D conversion is compeleted */
#define ADINT_ADSTIE            0x00000008      /* Enable A/D conversion complete for select mode */

/* bit field of ADFINT register */
#define ADFINT_ADFAS            0x00000001      /* Assert interrupt */

/* bit field of ADR0 register */
#define ADR0_DT0                0x00000FFF

/* bit field of ADR1 register */
#define ADR1_DT1                0x00000FFF

/* bit field of ADR2 register */
#define ADR2_DT2                0x00000FFF

/* bit field of ADR3 register */
#define ADR3_DT3                0x00000FFF

/* bit field of ADR4 register */
#define ADR4_DT4                0x00000FFF

/* bit field of ADR5 register */
#define ADR5_DT5                0x00000FFF

/* bit field of ADR6 register */
#define ADR6_DT6                0x00000FFF

/* bit field of ADR7 register */
#define ADR7_DT7                0x00000FFF


/*****************************************************/
/*    Standby Control Register                       */
/*****************************************************/
#define SBCR_BASE       0xB6400000              /* base address of Standby Control Register */
#define MASK            (SBCR_BASE +0x00)       /* Mask status register */
#define INTPC           (SBCR_BASE +0x04)       /* Core resume condition register */
#define SDRAMCKE        (SBCR_BASE +0x08)       /* SDRAM-CKE control register */
#define PLCLR           (SBCR_BASE +0x0C)       /* Core resume input latch clear register */
#define INTPCS          (SBCR_BASE +0x10)       /* Core resume input status latch register */
#define RESUMEIN        (SBCR_BASE +0x14)       /* Core resume input status register */
#define STBCS           (SBCR_BASE +0x18)       /* CS control register for stanby mode */

/* bit field of MASK register */
#define MASK_MASK               0x00000001

/* bit field of INTPC register */
#define INTPC_INTPC0            0x00000003      /* Resume condition depend on RESUME port */
#define INTPC_INTPC1            0x00000004      /* Resume condition depend on RTC interrupt */

/* bit field of SDRAMCKE register */
#define SDRAMCKE_SDRAMCKE       0x00000001      /* SDCKE output on stanby mode */

/* bit field of PLCLR register */
#define PLCLR_LCLR              0x00000001      /* Send reset signal for interanl power resume input latch  */

/* bit field of INTPCS register */
#define INTPCS_INTPCS0          0x00000001      /* Detect core resume input by RESUME port */
#define INTPCS_INTPCS1          0x00000002      /* Detect core resume input by RTC interrupt */

/* bit field of RESUMEIN register */
#define RESUMEIN_RESUME         0x00000001
#define RESUMEIN_RTCINT         0x00000002

/* bit field of STBCS register */
#define STBCS_ROMCSO            0x00000001      /* ROMCSN output level for standby mode */
#define STBCS_RAMCSO            0x00000002      /* RAMCSN output level for standby mode */
#define STBCS_IOCS0O            0x00000004      /* IOCS0N output level for standby mode */
#define STBCS_IOCS1O            0x00000008      /* IOCS1N output level for standby mode */