ml675050.h

OKI 675050 hardware accelerator sample program

#define DMAINTA_IREQ1           0x00000002      /* Channel 1 interrupt request */
#define DMAINTA_IREQ2           0x00000004      /* Channel 2 interrupt request */
#define DMAINTA_IREQ3           0x00000008      /* Channel 3 interrupt request */
#define DMAINTA_ISTA0           0x00000100      /* Channel 0 source / termination status */
#define DMAINTA_ISTA1           0x00000200      /* Channel 1 source / termination status */
#define DMAINTA_ISTA2           0x00000400      /* Channel 2 source / termination status */
#define DMAINTA_ISTA3           0x00000800      /* Channel 3 source / termination status */
#define DMAINTA_ISTP0           0x00010000      /* Channel 0 error cycle */
#define DMAINTA_ISTP1           0x00020000      /* Channel 1 error cycle */
#define DMAINTA_ISTP2           0x00040000      /* Channel 2 error cycle */
#define DMAINTA_ISTP3           0x00080000      /* Channel 3 error cycle */

/* bit field of DMACMSKA0 register */
#define DMACMSKA0_MSK           0x00000001      /* Channel 0 mask */

/* bit field of DMACTMODA0 register */
#define DMACTMODA0_ARQ          0x00000001      /* Transfer request auto/dreq */
#define DMACTMODA0_TSIZ         0x00000006      /* Transfer size */
#define DMACTMODA0_SDP          0x00000008      /* Source device type */
#define DMACTMODA0_DDP          0x00000010      /* Destination device type */
#define DMACTMODA0_BRQ          0x00000020      /* Bus request type */
#define DMACTMODA0_IMK          0x00000040      /* Interrupt mask */

/* bit field of DMACSIZA0 register */
#define DMACSIZA0_CSIZ          0x0001FFFF

/* bit field of DMACMSKA1 register */
#define DMACMSKA1_MSK           0x00000001      /* Channel 1 mask */

/* bit field of DMACTMODA1 register */
#define DMACTMODA1_ARQ          0x00000001      /* Transfer request auto/dreq */
#define DMACTMODA1_TSIZ         0x00000006      /* Transfer size */
#define DMACTMODA1_SDP          0x00000008      /* Source device type */
#define DMACTMODA1_DDP          0x00000010      /* Destination device type */
#define DMACTMODA1_BRQ          0x00000020      /* Bus request type */
#define DMACTMODA1_IMK          0x00000040      /* Interrupt mask */

/* bit field of DMACSIZA1 register */
#define DMACSIZA1_CSIZ          0x0001FFFF

/* bit field of DMACMSKA2 register */
#define DMACMSKA2_MSK           0x00000001      /* Channel 2 mask */

/* bit field of DMACTMODA2 register */
#define DMACTMODA2_ARQ          0x00000001      /* Transfer request auto/dreq */
#define DMACTMODA2_TSIZ         0x00000006      /* Transfer size */
#define DMACTMODA2_SDP          0x00000008      /* Source device type */
#define DMACTMODA2_DDP          0x00000010      /* Destination device type */
#define DMACTMODA2_BRQ          0x00000020      /* Bus request type */
#define DMACTMODA2_IMK          0x00000040      /* Interrupt mask */

/* bit field of DMACSIZA2 register */
#define DMACSIZA2_CSIZ          0x0001FFFF

/* bit field of DMACMSKA3 register */
#define DMACMSKA3_MSK           0x00000001      /* Channel 3 mask */

/* bit field of DMACTMODA3 register */
#define DMACTMODA3_ARQ          0x00000001      /* Transfer request auto/dreq */
#define DMACTMODA3_TSIZ         0x00000006      /* Transfer size */
#define DMACTMODA3_SDP          0x00000008      /* Source device type */
#define DMACTMODA3_DDP          0x00000010      /* Destination device type */
#define DMACTMODA3_BRQ          0x00000020      /* Bus request type */
#define DMACTMODA3_IMK          0x00000040      /* Interrupt mask */

/* bit field of DMACSIZA3 register */
#define DMACSIZA3_CSIZ          0x0001FFFF

/* bit field of DMAMODB register */
#define DMAMODB_PRI             0x00000001      /* Channel Priority */

/* bit field of DMASTAB register */
#define DMASTAB_STA0            0x00000001      /* Channel 0 Status */
#define DMASTAB_STA1            0x00000002      /* Channel 1 Status */

/* bit field of DMAINTB register */
#define DMAINTB_IREQ0           0x00000001      /* Channel 0 interrupt request */
#define DMAINTB_IREQ1           0x00000002      /* Channel 1 interrupt request */
#define DMAINTB_ISTA0           0x00000100      /* Channel 0 source / termination status */
#define DMAINTB_ISTA1           0x00000200      /* Channel 1 source / termination status */
#define DMAINTB_ISTP0           0x00010000      /* Channel 0 Error cycle */
#define DMAINTB_ISTP1           0x00020000      /* Channel 1 Error cycle */

/* bit field of DMACMSKB0 register */
#define DMACMSKB0_MSK           0x00000001      /* Channel 0 mask */

/* bit field of DMACTMODB0 register */
#define DMACTMODB0_ARQ          0x00000001      /* Transfer request auto/dreq */
#define DMACTMODB0_TSIZ         0x00000006      /* Transfer size */
#define DMACTMODB0_SDP          0x00000008      /* Source device type */
#define DMACTMODB0_DDP          0x00000010      /* Destination device type */
#define DMACTMODB0_BRQ          0x00000020      /* Bus request type */
#define DMACTMODB0_IMK          0x00000040      /* Interrupt mask */

/* bit field of DMACSIZB0 register */
#define DMACSIZB0_CSIZ          0x0001FFFF

/* bit field of DMACMSKB1 register */
#define DMACMSKB1_MSK           0x00000001      /* Channel 1 mask */

/* bit field of DMACTMODB1 register */
#define DMACTMODB1_ARQ          0x00000001      /* Transfer request auto/dreq */
#define DMACTMODB1_TSIZ         0x00000006      /* Transfer size */
#define DMACTMODB1_SDP          0x00000008      /* Source device type */
#define DMACTMODB1_DDP          0x00000010      /* Destination device type */
#define DMACTMODB1_BRQ          0x00000020      /* Bus request type */
#define DMACTMODB1_IMK          0x00000040      /* Interrupt mask */

/* bit field of DMACSIZB1 register */
#define DMACSIZB1_CSIZ          0x0001FFFF


/*****************************************************/
/*    Extended Interrupt Control register            */
/*****************************************************/
#define EIC_BASE        0x7BF00000              /* base address of Extended Interrupt Control register */
#define EXIRS           (EIC_BASE+0x00)         /* Extended interrupt size register */
#define EXIRCL          (EIC_BASE+0x04)         /* Extended interrupt clear register */
#define EXIRQA          (EIC_BASE+0x10)         /* Extended interrupt IRQ register A */
#define EXILCA          (EIC_BASE+0x18)         /* Extended interrupt IRQ level control register A */
#define EXIRQSA         (EIC_BASE+0x1C)         /* Extended interrupt IRQ status register A */
#define EXIRQB          (EIC_BASE+0x20)         /* Extended interrupt IRQ register B */
#define EXIDM           (EIC_BASE+0x24)         /* Extended interrupt detection mode setting register */
#define EXILCB          (EIC_BASE+0x28)         /* Extended interrupt IRQ level control register B */
#define EXIRQSB         (EIC_BASE+0x2C)         /* Extended interrupt IRQ status register B */
#define EXIRQC          (EIC_BASE+0x30)         /* Extended interrupt IRQ register C */
#define EXILCC          (EIC_BASE+0x38)         /* Extended interrupt IRQ level control register C */
#define EXIRQSC         (EIC_BASE+0x3C)         /* Extended interrupt IRQ status register C */
#define EXFIQ           (EIC_BASE+0x80)         /* Extended interrupt FIQ register */
#define EXFIDM          (EIC_BASE+0x84)         /* Extended interrupt FIQ detection mode setting register */

/* bit field of EXIRCL register */
#define EXIRCL_IRN              0x0000003F      /* Interrupt number */

/* bit field of EXIRQA register */
#define EXIRQA_IRQ16            0x00000001
#define EXIRQA_IRQ17            0x00000002
#define EXIRQA_IRQ18            0x00000004
#define EXIRQA_IRQ19            0x00000008
#define EXIRQA_IRQ20            0x00000010
#define EXIRQA_IRQ21            0x00000020
#define EXIRQA_IRQ22            0x00000040
#define EXIRQA_IRQ23            0x00000080
#define EXIRQA_IRQ24            0x00000100
#define EXIRQA_IRQ25            0x00000200
#define EXIRQA_IRQ26            0x00000400
#define EXIRQA_IRQ27            0x00000800
#define EXIRQA_IRQ28            0x00001000
#define EXIRQA_IRQ29            0x00002000
#define EXIRQA_IRQ30            0x00004000
#define EXIRQA_IRQ31            0x00008000

/* bit field of EXILCA register */
#define EXILCA_ILC16            0x00000007      /* IR16,IR17 */
#define EXILCA_ILC18            0x00000070      /* IR18,IR19 */
#define EXILCA_ILC20            0x00000700      /* IR20,IR21 */
#define EXILCA_ILC22            0x00007000      /* IR22,IR23 */
#define EXILCA_ILC24            0x00070000      /* IR24,IR25 */
#define EXILCA_ILC26            0x00700000      /* IR26,IR27 */
#define EXILCA_ILC28            0x07000000      /* IR28,IR28 */
#define EXILCA_ILC30            0x70000000      /* IR29,IR30 */

/* bit field of EXIRQSA register */
#define EXIRQSA_IRQ16           0x00000001
#define EXIRQSA_IRQ17           0x00000002
#define EXIRQSA_IRQ18           0x00000004
#define EXIRQSA_IRQ19           0x00000008
#define EXIRQSA_IRQ20           0x00000010
#define EXIRQSA_IRQ21           0x00000020
#define EXIRQSA_IRQ22           0x00000040
#define EXIRQSA_IRQ23           0x00000080
#define EXIRQSA_IRQ24           0x00000100
#define EXIRQSA_IRQ25           0x00000200
#define EXIRQSA_IRQ26           0x00000400
#define EXIRQSA_IRQ27           0x00000800
#define EXIRQSA_IRQ28           0x00001000
#define EXIRQSA_IRQ29           0x00002000
#define EXIRQSA_IRQ30           0x00004000
#define EXIRQSA_IRQ31           0x00008000

/* bit field of EXIRQB register */
#define EXIRQB_IRQ32            0x00000001
#define EXIRQB_IRQ33            0x00000002
#define EXIRQB_IRQ34            0x00000004
#define EXIRQB_IRQ35            0x00000008
#define EXIRQB_IRQ36            0x00000010
#define EXIRQB_IRQ37            0x00000020
#define EXIRQB_IRQ38            0x00000040
#define EXIRQB_IRQ39            0x00000080
#define EXIRQB_IRQ40            0x00000100
#define EXIRQB_IRQ41            0x00000200
#define EXIRQB_IRQ42            0x00000400
#define EXIRQB_IRQ43            0x00000800
#define EXIRQB_IRQ44            0x00001000
#define EXIRQB_IRQ45            0x00002000
#define EXIRQB_IRQ46            0x00004000
#define EXIRQB_IRQ47            0x00008000

/* bit field of EXIDM register */
#define EXIDM_IDM32             0x00000001      /* Select IR32 interrupt detection mode  */
#define EXIDM_IDM34             0x00000004      /* Select IR34 interrupt detection mode  */
#define EXIDM_IDM36             0x00000010      /* Select IR36 interrupt detection mode  */
#define EXIDM_IDM38             0x00000040      /* Select IR38 interrupt detection mode  */
#define EXIDM_IDM40             0x00000100      /* Select IR40 interrupt detection mode  */
#define EXIDM_IDM42             0x00000400      /* Select IR42 interrupt detection mode  */
#define EXIDM_IDM44             0x00001000      /* Select IR44 interrupt detection mode  */

/* bit field of EXILCB register */
#define EXILCB_ILC32            0x00000007      /* IR32,IR33 */
#define EXILCB_ILC34            0x00000070      /* IR34,IR35 */
#define EXILCB_ILC36            0x00000700      /* IR36,IR37 */
#define EXILCB_ILC38            0x00007000      /* IR38,IR39 */
#define EXILCB_ILC40            0x00070000      /* IR40,IR41 */
#define EXILCB_ILC42            0x00700000      /* IR42,IR43 */
#define EXILCB_ILC44            0x07000000      /* IR44,IR45 */
#define EXILCB_ILC46            0x70000000      /* IR46,IR47 */

/* bit field of EXIRQSB register */
#define EXIRQSB_IRQ32           0x00000001
#define EXIRQSB_IRQ33           0x00000002
#define EXIRQSB_IRQ34           0x00000004
#define EXIRQSB_IRQ35           0x00000008
#define EXIRQSB_IRQ36           0x00000010
#define EXIRQSB_IRQ37           0x00000020
#define EXIRQSB_IRQ38           0x00000040