bcddecoder.vhd

来自「该程序是基于FPGA的的设计」· VHDL 代码 · 共 26 行

--用于公阳连接
library ieee;
use ieee.std_logic_1164.all;
entity BCDdecoder is
	port
	(
		BCDdata:in std_logic_vector(3 downto 0);
		y:out std_logic_vector(7 downto 0)
	);
end BCDdecoder;
architecture BCDdecoder_arc of BCDdecoder is
	begin
		with BCDdata select
		y<="10111111" when "0000",
		   "11111001" when "0001",
		   "10100100" when "0010",
		   "10110000" when "0011",
		   "10011001" when "0100",
		   "10010010" when "0101",
		   "10000010" when "0110",
		   "11111000" when "0111",
		   "10000000" when "1000",
		   "10011000" when "1001",
		   "00000000" when others;
end BCDdecoder_arc;