📄 pciad.asm
字号:
.def start
.sect "code"
start:
;.sect "vectors"
RESET: B.S2 MAIN
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NMI: B.S2 ERROR
NOP
NOP
NOP
NOP
NOP
NOP
NOP
AINT: B.S2 ERROR
NOP
NOP
NOP
NOP
NOP
NOP
NOP
MSGINT: B.S2 ERROR
NOP
NOP
NOP
NOP
NOP
NOP
INT4: B .S2 startint
NOP 5
ERROR: B.S2 ERROR
NOP 5
.sect "op"
startint:
MVC .S2 CSR,B5 ;CSR---B5
CLR .S2 B5,0,0,B5 ;BIT0=0
MVC .S2 B5,CSR ;GIE=0 mask int
SUB .L1 A8,1,A8
MV .L1 A8,A1
[A1] B .S1 sta2
NOP 5
MVK .S1 adctlptr, A3 ;
MVKH .S1 adctlptr,A3
MVK .S1 0x0, A1 ; STOP a/d
MVKH .S1 0x0,A1
STW .D1 A1,*A3
MVK .S1 adram, A4 ;
MVKH .S1 adram,A4
MVK .S1 0x0fff, A2 ;
MVKH .S1 0x0,A2
MVK .S1 0X1000,A1
MVK .S1 0X800,A11
MVK .S1 0X10, A3 ;
MVKH .S1 interdata, A3
LOOPLD: LDW .D1 *A4++,A6 ;READ DATA
NOP 4
AND .L1 A6,A2,A10
NOP 4
SUB .L1 A10,A11,A10
STW .D1 A10,*A3++ ;WRITE
SUB .L1 A1,1,A1
[A1] B .S1 LOOPLD
NOP 5
B .S2 IRP
NOP 5
sta2: MVC .S2 CSR,B5
OR .L2 1,B5,B5
MVC .S2 B5,CSR ; int enable
B .S2 IRP
NOP 5
.sect "init"
sdptr .set 0x2000000 ; SDRAM adr.
flashptr .set 0x01400000 ; CE1 LINE PORT
emifcom .set 0x1800000 ; EMIF global reg.
interdata .set 0x80000000 ; interdata
emifctl .set 0x37E9 ;emif globle control :SBSRAM=1/2 CLK
dada7 .set 0x37ED ; SBSRAM= 1x clk
sd_time .set 0x07238000 ;sdram control
sbramctl .set 0x40 ; CE0 control
asramctl .set 0x0B300A21 ; CE1 control ;10MHZ
sbramptr .set 0x400000 ; SBSRAM adr. ce0
data4 .set 0x400000 ;sdram length
datalen .set 0x20000 ; data len ce0
data3 .set 0x1000 ;data len dual-ram
adram .set 0x1400000 ;dual ram adr. ce3
adctlptr .set 0x3380000 ; .set 0x3004000 ;a/d cntl adr.
daright .set 0X5555AAAA ;CRORRECT INDEX
daerror .set 0X34464644 ;ERROR INDEX
MAIN: MVK .S1 emifcom,A1 ;EMIF INIT
MVKH .S1 emifcom,A1
MVK .S1 emifctl,A2
STW .D1 A2,*A1 ;GLOBE CONTROL REG.
MVK .S1 0x30,A2
MVKH .S1 0x30,A2
STW .D1 A2,*+A1[4] ; CE2 CONTROL REG.
MVK .S1 0x410,A2 ;0x410
MVKH .S1 0x410,A2
STW .D1 A2,*+A1[7] ; SDRAM TIMING REG.
MVK .S1 sd_time,A2
MVKH .S1 sd_time,A2
STW .D1 A2,*+A1[6] ; SDRAM CONTROL REG.
MVK .S1 0X40,A2
MVKH .S1 0X40,A2
STW .D1 A2,*+A1[2] ; CE0 CONTRPL REG.
MVK .S1 asramctl,A2
MVKH .S1 asramctl,A2
STW .D1 A2,*+A1[1] ; CE1 CONTROL REG.
NOP 4
STW .D1 A2,*+A1[5] ; CE3 CONTROL REG
MVC .S2 CSR,B5 ;CSR---B5
CLR .S2 B5,0,0,B5 ;BIT0=0
MVC .S2 B5,CSR ;GIE=0 mask int
MVK .S1 0,A2
MVK .S1 interdata,A3 ; 0x80000000
MVKH .S1 interdata,A3
MVK .S1 data3,A1 ; WRITE LENGTH
MVKH .S1 data3,A1
lclr: STW .D1 A2,*A3++ ;CLEAR
SUB .L1 A1,1,A1
[A1] B .S1 lclr
NOP 5
MVK .S1 0,A2
TEST: MVK .S1 interdata,A5 ; SDRAM ADR.1
MVKH .S1 interdata,A5
MVK .S1 sdptr,A3 ; SDRAM ADR.1
MVKH .S1 sdptr,A3
MVK .S1 data4,A1 ; WRITE LENGTH
MVKH .S1 data4,A1
s0: STW .D1 A2,*A3++ ;WRITE
NOP 5
ADD .S1 A2,1,A2
SUB .L1 A1,1,A1
[A1] B .S1 s0
NOP 5
MVK .S1 0,A2
MVKH .S1 0,A2
MVK .S1 sdptr,A3 ; SDRAM ADR.1
MVKH .S1 sdptr,A3
MVK .S1 data4,A10 ; READ LENGTH
MVKH .S1 data4,A10
LOOP: LDW .D1 *A3++, A4 ;READ
NOP 5
CMPEQ .L1 A4,A2,A1
NOP 5
[!A1] B .S1 SDERROR
NOP 5
ADD .S1 A2,1,A2
SUB .L1 A10,1,A10
MV .L1 A10, A1
[A1] B .S1 LOOP
NOP 5
LDW .D1 *A5,A1
NOP 5
ADD .S1 A1,1,A1
NOP 5
STW .D1 A1,*A5
NOP 5
B .s1 sbnext
NOP 5
SDERROR: LDW .D1 *+A5[0X10],A1
NOP 5
ADD .S1 A1,1,A1
NOP 5
STW .D1 A1,*+A5[0X10]
sbnext: MVK .S1 sbramptr,A3 ; SDRAM ADR.1
MVKH .S1 sbramptr,A3
MV .S1 A2,A6
MVK .S1 datalen,A1 ; WRITE LENGTH
MVKH .S1 datalen,A1
ss1: STW .D1 A2,*A3++ ;WRITE
ADD .S1 A2,1,A2
SUB .L1 A1,1,A1
[A1] B .S1 ss1
NOP 5
MVK .S1 datalen,A10 ; READ LENGTH
MVKH .S1 datalen,A10
MVK .S1 sbramptr,A3 ; SDRAM ADR.1
MVKH .S1 sbramptr,A3
LOOP1: LDW .D1 *A3++, A4 ;READ
NOP 5
SUB .L1 A4,A6,A1
[A1] B .S1 SBERROR
NOP 5
ADD .S1 A6,1,A6
SUB .L1 A10,1,A10
MV .L1 A10,A1
[A1] B .S1 LOOP1
nop 5
LDW .D1 *+A5[4],A1
NOP 5
ADD .S1 A1,1,A1
NOP 5
STW .D1 A1,*+A5[4]
NOP 5
B .s1 duramnext
NOP 5
SBERROR: LDW .D1 *+A5[0X14],A1
NOP 5
ADD .S1 A1,1,A1
NOP 5
STW .D1 A1,*+A5[0X14]
NOP 5
duramnext: MVK .S1 adram,A3 ; SDRAM ADR.1
MVKH .S1 adram,A3
MV .S1 A6, A2
MVK .S1 data3,A1 ; WRITE LENGTH
MVKH .S1 data3,A1
ss2: STW .D1 A2,*A3++ ;WRITE
nop 5
ADD .S1 A2,1,A2
SUB .L1 A1,1,A1
[A1] B .S1 ss2
NOP 5
MVK .S1 data3,A10 ; READ LENGTH
MVKH .S1 data3,A10
MVK .S1 adram,A3 ; SDRAM ADR.1
MVKH .S1 adram,A3
LOOP2: LDW .D1 *A3++, A4 ;READ
NOP 5
SUB .L1 A4,A6,A1
[A1] B .S1 ADERROR
NOP 5
ADD .S1 A6,1,A6
SUB .L1 A10,1,A10
MV .L1 A10,A1
[A1] B .S1 LOOP2
nop 5
LDW .D1 *+A5[8],A1
NOP 5
ADD .S1 A1,1,A1
NOP 5
STW .D1 A1,*+A5[8]
NOP 5
B MEMEND
NOP 5
ADERROR: LDW .D1 *+A5[0X18],A1
ADD .S1 A1,1,A1
NOP 5
STW .D1 A1,*+A5[0X18]
NOP 5
MEMEND: MVK .S1 0,A9
MVK .S2 0083h,B3 ;bit7=1
MVC .S2 IER,B4 ;IER---B4
OR .L2 B3,B4,B4 ; SET BIT 7
MVC .S2 B4,IER ; WRITE IER
MVK .S2 0X19C0004,B8 ;INTERRUPT SELECTOR REG.
MVKH .S2 0X19C0004,B8
MVK .S2 0X00070000,B9 ;SELECT EXT_INT7
MVKH .S2 0X00070000,B9
STW .D2 B9,*B8
MVK .S2 0X19C0008,B8 ; SET THE POLARITY
MVKH .S2 0X19C0008,B8
MVK .S2 0X00000008,B9 ;SET XIP7
STW .D2 B9,*B8
MVC .S2 CSR,B5 ; GET CSR---B5
OR .L2 1,B5,B5 ; BIT0= '1'
MVC .S2 B5,CSR ;GIE=1
MVK .S1 adctlptr,A3
MVKH .S1 adctlptr,A3
MVK .S1 0x21, A1 ; start a/d 4k
MVKH .S1 0x0,A1
STW .D1 A1,*A3
NOP 5
MVK .S1 0x0, A9 ; clear a9
MVKH .S1 0x0,A9
MVK .S1 0x40, A8 ; clear a9
MVKH .S1 0x0,A8
loop34: B TEST ;WAIT FOR INT7
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -