📄 board.c
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// calculate nearest freq without going over
if (freq % 10)
freq = ((freq/10) * 10);
// set global variable
cpuFreq = freq;
// initialize clock generator
clock_init(EVM_OSC, cpuFreq, PLL_DIV_2);
}
/*****************************************************************************/
/* u16 brd_get_cpu_freq() */
/* */
/* This routine returns the CPU frequency */
/* */
/* Parameters: */
/* - None */
/* */
/* Return: */
/* - frequnecy in MHz */
/* */
/* Notes: */
/*****************************************************************************/
u16 brd_get_cpu_freq()
{
return cpuFreq;
}
/*****************************************************************************/
/* void brd_emif_init() */
/* */
/* This routine initializes the EMIF registers */
/* */
/* Parameters: */
/* - None */
/* */
/* Return: */
/* - None */
/* */
/* Notes: CE2 space, where the daughter board resides, is not configured */
/* so users will need to setup this space when a daughter board is */
/* present. */
/*****************************************************************************/
void brd_emif_init()
{
EmifSpaceCtrl ce0, ce1, ce3;
u16 writeSetup, writeStrobe, writeHold;
u16 readSetup, readStrobe, readHold, freq;
u16 gctrl;
if (cpuFreq > 120)
gctrl = (1 << MEMCEN) | (1 << MEMFREQ);
else
gctrl = (1 << MEMCEN);
//1M SBSRAM. if MTYPE selects SBSRAM, remaining
//fields (ctrl1, ctrl2, ctrl3) do not apply
ce0.ctrl1 = (MTYPE_32SBSRAM << MTYPE);
ce0.ctrl2 = 0;
ce0.ctrl3 = 0;
freq = cpuFreq / 10;
readSetup = READ_SETUP_NS;
readStrobe = (u16)((READ_STROBE_NS * freq) / 100) + 1;
readHold = (u16)((READ_HOLD_NS * freq) / 100) + 1;
writeSetup = WRITE_SETUP_NS;
writeStrobe = (u16)((WRITE_STROBE_NS * freq) / 100) + 1;
writeHold = (u16)((WRITE_HOLD_NS * freq) / 100) + 1;
//1M Flash
#if 0
ce1.ctrl1 = (MTYPE_32ASYNC << MTYPE) |
(0xf << READ_SETUP) |
(0x3f << READ_STROBE) |
(0x3 << READ_HOLD);
ce1.ctrl2 = (0xf << WRITE_SETUP) |
(0x3f << WRITE_STROBE) |
(0x3 << WRITE_HOLD) |
(0x3 << EXT_HOLD_WRITE) |
(0x3 << EXT_HOLD_READ);
ce1.ctrl3 = 0;
#else
ce1.ctrl1 = (MTYPE_32ASYNC << MTYPE) |
(readSetup << READ_SETUP) |
(readStrobe << READ_STROBE) |
(readHold << READ_HOLD);
ce1.ctrl2 = (writeSetup << WRITE_SETUP) |
(writeStrobe << WRITE_STROBE) |
(writeHold << WRITE_HOLD) |
(0x3 << EXT_HOLD_WRITE) |
(u16)(0x3 << EXT_HOLD_READ);
ce1.ctrl3 = 0;
#endif
//CPLD
ce3.ctrl1 = (MTYPE_16ASYNC << MTYPE) |
(0xf << READ_SETUP) |
(0x3f << READ_STROBE) |
(0x3 << READ_HOLD);
ce3.ctrl2 = (0xf << WRITE_SETUP) |
(0x3f << WRITE_STROBE) |
(0x3 << WRITE_HOLD) |
(0x3 << EXT_HOLD_WRITE) |
(0x3 << EXT_HOLD_READ);
ce3.ctrl3 = 0;
//4M Daughter board in ce2 space defaulting for now
//CPLD registers in ce3 spcae defaulting for now
emif_init(gctrl, &ce0, &ce1, (EmifSpaceCtrl *)0, &ce3, (EmifSdramCtrl *)0);
}
/*****************************************************************************/
/* void brd_interrupt_host() */
/* */
/* This routine interrupts the host application . */
/* */
/* Parameters: */
/* - None */
/* Return: */
/* - None */
/* */
/* Notes: */
/* */
/*****************************************************************************/
void brd_interrupt_host()
{
// algebraic instructions
//asm("\tbit(st3, #st3_hint) = #0");
//asm("\tbit(st3, #st3_hint) = #1");
asm("\tBCLR #st3_hint, st3_55");
asm("\tBSET #st3_hint, st3_55");
}
/*****************************************************************************/
/* void brd_busy_delay(u16 delay) */
/* */
/* This routine delays execution by specified delay . */
/* */
/* Parameters: */
/* - delay - delay in multiples of 64K loop count */
/* */
/* Return: */
/* - None */
/* */
/* Notes: */
/* */
/*****************************************************************************/
void brd_busy_delay(u16 delay)
{
volatile u16 temp;
while (delay--)
{
temp = 0xffff;
while(temp--);
}
}
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