📄 mcbsp55x.h
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#define XCE7 7
#define XCE7_SZ 1
#define XCE6 6
#define XCE6_SZ 1
#define XCE5 5
#define XCE5_SZ 1
#define XCE4 4
#define XCE4_SZ 1
#define XCE3 3
#define XCE3_SZ 1
#define XCE2 2
#define XCE2_SZ 1
#define XCE1 1
#define XCE1_SZ 1
#define XCE0 0
#define XCE0_SZ 1
/*********************************************************************/
/* Define bit fields for Pin Control Register */
/*********************************************************************/
#define XIOEN 13
#define XIOEN_SZ 1
#define RIOEN 12
#define RIOEN_SZ 1
#define FSXM 11
#define FSXM_SZ 1
#define FSRM 10
#define FSRM_SZ 1
#define CLKXM 9
#define CLKXM_SZ 1
#define CLKRM 8
#define CLKRM_SZ 1
#define SCLKME 7
#define SCLKME_SZ 1
#define CLKS_STAT 6
#define CLKS_STAT_SZ 1
#define DX_STAT 5
#define DX_STAT_SZ 1
#define DR_STAT 4
#define DR_STAT_SZ 1
#define FSXP 3
#define FSXP_SZ 1
#define FSRP 2
#define FSRP_SZ 1
#define CLKXP 1
#define CLKXP_SZ 1
#define CLKRP 0
#define CLKRP_SZ 1
/*********************************************************************/
/* CONFIGURATION REGISTER BIT and BITFIELD values */
/*********************************************************************/
#define MCBSP_RX 1
#define MCBSP_TX 2
#define MCBSP_BOTH 3
//Serial Port Control Register SPCR1
#define DLB_ENABLE 0x01 //Enable Digital Loopback Mode
#define DLB_DISABLE 0x00 //Disable Digital Loopback Mode
#define RXJUST_RJZF 0x00 //Receive Right Justify Zero Fill
#define RXJUST_RJSE 0x01 //Receive Right Justify Sign Extend
#define RXJUST_LJZF 0x02 //Receive Left Justify Zero Fill
#define CLK_STOP_DISABLED 0x00 //Normal clocking for non-SPI mode
#define CLK_START_WO_DELAY 0x02 //Clock starts without delay
#define CLK_START_W_DELAY 0x03 //Clock starts with delay
#define DX_ENABLE_OFF 0x00 //no extra delay for turn-on time
#define DX_ENABLE_ON 0x01 //enable extra delay for turn-on time
#define ABIS_DISABLE 0x00 //A-bis mode is disabled
#define ABIS_ENABLE 0x01 //A-bis mode is enabled
//Serial Port Control Registers SPCR1 and SPCR2
#define INTM_RDY 0x00 //R/X INT driven by R/X RDY
#define INTM_BLOCK 0x01 //R/X INT driven by new multichannel blk
#define INTM_FRAME 0x02 //R/X INT driven by new frame sync
#define INTM_SYNCERR 0x03 //R/X INT generated by R/X SYNCERR
#define RX_RESET 0x00 //R or X in reset
#define RX_ENABLE 0x01 //R or X enabled
//Serial Port Control Register SPCR2
#define SP_FREE_OFF 0x00 //Free running mode is diabled
#define SP_FREE_ON 0x01 //Free running mode is enabled
#define SOFT_DISABLE 0x00 //SOFT mode is disabled
#define SOFT_ENABLE 0x01 //SOFT mode is enabled
#define FRAME_GEN_RESET 0x00 //Frame Synchronization logic is reset
#define FRAME_GEN_ENABLE 0x01 //Frame sync signal FSG is generated
#define SRG_RESET 0x00 //Sample Rate Generator is reset
#define SRG_ENABLE 0x01 //Sample Rate Generator is enabled
//Pin Control Register PCR
#define IO_DISABLE 0x00 //No General Purpose I/O Mode
#define IO_ENABLE 0x01 //General Purpose I/0 Mode enabled
#define CLKR_POL_RISING 0x01 //R Data Sampled on Rising Edge of CLKR
#define CLKR_POL_FALLING 0x00 //R Data Sampled on Falling Edge of CLKR
#define CLKX_POL_RISING 0x00 //X Data Sent on Rising Edge of CLKX
#define CLKX_POL_FALLING 0x01 //X Data Sent on Falling Edge of CLKX
#define FSYNC_POL_HIGH 0x00 //Frame Sync Pulse Active High
#define FSYNC_POL_LOW 0x01 //Frame Sync Pulse Active Low
#define CLK_MODE_EXT 0x00 //Clock derived from external source
#define CLK_MODE_INT 0x01 //Clock derived from internal source
#define FSYNC_MODE_EXT 0x00 //Frame Sync derived from external src
#define FSYNC_MODE_INT 0x01 //Frame Sync dervived from internal src
#define IDLE_ENABLE 0x01 //Stop all McBsp clocks when in IDLE mode
#define IDLE_DISABLE 0x00 //Do not stop all McBsp clocks when in IDLE mode
//Transmit Receive Control Register XCR/RCR
#define SINGLE_PHASE 0x00 //Selects single phase frames
#define DUAL_PHASE 0x01 //Selects dual phase frames
#define MAX_FRAME_LENGTH 0x7f //maximum number of words per frame
#define WORD_LENGTH_8 0x00 //8 bit word length (requires filling)
#define WORD_LENGTH_12 0x01 //12 bit word length ""
#define WORD_LENGTH_16 0x02 //16 bit word length ""
#define WORD_LENGTH_20 0x03 //20 bit word length ""
#define WORD_LENGTH_24 0x04 //24 bit word length ""
#define WORD_LENGTH_32 0x05 //32 bit word length (matches DRR DXR sz
#define MAX_WORD_LENGTH 0x20 //maximum number of bits per word
#define NO_COMPAND_MSB_1ST 0x00 //No Companding, Data XFER starts w/MSb
#define NO_COMPAND_LSB_1ST 0x01 //No Companding, Data XFER starts w/LSb
#define COMPAND_ULAW 0x02 //Compand ULAW, 8 bit word length only
#define COMPAND_ALAW 0x03 //Compand ALAW, 8 bit word length only
#define FRAME_IGNORE 0x01 //Ignore frame sync pulses after 1st
#define NO_FRAME_IGNORE 0x00 //Utilize frame sync pulses
#define DATA_DELAY0 0x00 //1st bit in same clk period as fsync
#define DATA_DELAY1 0x01 //1st bit 1 clk period after fsync
#define DATA_DELAY2 0x02 //1st bit 2 clk periods after fsync
//Sample Rate Generator Register SRGR
//Clock mode (ext. / int.) see PCR
#define MAX_SRG_CLK_DIV 0xff //max value to divide Sample Rate Gen Cl
#define MAX_FRAME_WIDTH 0xff //maximum FSG width in CLKG periods
#define MAX_FRAME_PERIOD 0x0fff //FSG period in CLKG periods
#define FSX_DXR_TO_XSR 0x00 //Transmit FSX due to DXR to XSR copy
#define FSX_FSG 0x01 //Transmit FSX due to FSG
#define CLKS_POL_FALLING 0x00 //falling edge generates CLKG and FSG
#define CLKS_POL_RISING 0x01 //rising edge generates CLKG and FSG
#define GSYNC_OFF 0x00 //CLKG always running
#define GSYNC_ON 0x01 //CLKG and FSG synch'ed to FSR
//Multi-channel Control Register 1 and 2 MCR1/2
#define RMCM_CHANNEL_ENABLE 0x00 //all 128 channels enabled
#define RMCM_CHANNEL_DISABLE 0x01 //all channels disabled, selected by
//enabling RP(A-H)BLK, RCER(A-H)
#define XMCM_CHANNEL_DX_DRIVEN 0x00 //transmit data over DX pin for as many
//number of words as required
#define XMCM_XCER_CHAN_TO_DXR 0x01 //selected channels written to DXR
#define XMCM_ALL_WORDS_TO_DXR 0x02 //all words copied to DXR(1/2),
//DX only driven for selected words
#define XMCM_CHANNEL_SYM_R/X 0x03 //symmetric transmit and receive
//operation
#define MCM_128CHANNEL_DISABLE 0x01 //Normal mode 32 channels enabled
#define MCM_128CHANNEL_ENABLE 0x01 //Enable all 128 channels
/********* Macro Definitions **************************************/
/******************************************************************/
/******************************************************************/
/* MCBSP_ENABLE(unsigned short port, unsigned short type) - */
/* starts serial port receive and/or transmit */
/* type= 1 rx, type= 2 tx, type= 3 both */
/******************************************************************/
#define MCBSP_ENABLE(port,mode) \
{SPCR1(port) |= (mode & 1); \
SPCR2(port) |= ((mode >> 1) & 1);}
/******************************************************************/
/* MCBSP_TX_RESET() - reset transmit side of serial port */
/* */
/******************************************************************/
#define MCBSP_TX_RESET(port) \
SPCR2(port) &= ~(1<<XRST)
/******************************************************************/
/* MCBSP_RX_RESET() - reset receive side of serial port */
/* */
/******************************************************************/
#define MCBSP_RX_RESET(port) \
SPCR1(port) &= ~(1<<RRST)
/******************************************************************/
/* MCBSP_IO_ENABLE() - place port in general purpose I/O mode */
/******************************************************************/
#define MCBSP_IO_ENABLE(port) \
{ MCBSP_TX_RESET(port); MCBSP_RX_RESET(port); \
PCR(port) |= (0x0003 << RIOEN);}
/******************************************************************/
/* MCBSP_IO_DISABLE() - take port out of general purpose I/O mode */
/******************************************************************/
#define MCBSP_IO_DISABLE(port) \
PCR(port) &= ~(0x0003 << RIOEN)
/******************************************************************/
/* MCBSP_FRAME_SYNC_ENABLE - sets FRST bit in SPCR */
/******************************************************************/
#define MCBSP_FRAME_SYNC_ENABLE(port) \
SPCR2(port) |= (1<<FRST)
/******************************************************************/
/* MCBSP_FRAME_SYNC_RESET - clrs FRST bit in SPCR */
/******************************************************************/
#define MCBSP_FRAME_SYNC_RESET(port) \
SPCR2(port) &= ~(1<<FRST)
/******************************************************************/
/* MCBSP_SAMPLE_RATE_ENABLE - sets GRST bit in SPCR */
/******************************************************************/
#define MCBSP_SAMPLE_RATE_ENABLE(port) \
SPCR2(port) |= (1<<GRST)
/******************************************************************/
/* MCBSP_SAMPLE_RATE_RESET - clrs GRST bit in SPCR */
/******************************************************************/
#define MCBSP_SAMPLE_RATE_RESET(port) \
SPCR2(port) &= ~(1<<GRST)
/******************************************************************/
/* MCBSP_RRDY - returns selected ports RRDY */
/******************************************************************/
#define MCBSP_RRDY(port) \
((SPCR1(port) >> RRDY) & 0x1)
/******************************************************************/
/* MCBSP_XRDY - returns selected ports XRDY */
/******************************************************************/
#define MCBSP_XRDY(port) \
((SPCR2(port) >> XRDY) & 0x1)
/******************************************************************/
/* MCBSP_LOOPBACK_ENABLE - places selected port in loopback */
/******************************************************************/
#define MCBSP_LOOPBACK_ENABLE(port) \
SPCR1(port) |= (1<<DLB)
/******************************************************************/
/* MCBSP_LOOPBACK_DISABLE - takes port out of DLB */
/******************************************************************/
#define MCBSP_LOOPBACK_DISABLE(port) \
SPCR1(port) &= ~(1<<DLB)
/******************************************************************/
/* Structure definitions */
/******************************************************************/
typedef struct _McBspConfig
{
unsigned int port;
unsigned int spcr1;
unsigned int spcr2;
unsigned int rcr1;
unsigned int rcr2;
unsigned int xcr1;
unsigned int xcr2;
unsigned int srgr1;
unsigned int srgr2;
unsigned int mcr1;
unsigned int mcr2;
unsigned int pcr;
unsigned int rcera;
unsigned int xcera;
unsigned int rcerb;
unsigned int xcerb;
unsigned int rcerc;
unsigned int xcerc;
unsigned int rcerd;
unsigned int xcerd;
unsigned int rcere;
unsigned int xcere;
unsigned int rcerf;
unsigned int xcerf;
unsigned int rcerg;
unsigned int xcerg;
unsigned int rcerh;
unsigned int xcerh;
} McBspConfig, *PMcBspConfig;
/****************************************************************************/
/* FUNCTION DEFINITIONS */
/****************************************************************************/
void mcbsp_init(PMcBspConfig pBsp);
#endif //_MCBSP55X_H_
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