mcbsp55x.h

Real-Time Digital Signal Processing Implementations, Applications, and Experiments with the TMS320C

#define SPCR22_ADDR			(DRR22_ADDR+4)
#define SPCR22      		*(ioport volatile unsigned int *)SPCR22_ADDR

#define SPCR12_ADDR			(DRR22_ADDR+5)
#define SPCR12      		*(ioport volatile unsigned int *)SPCR12_ADDR

#define RCR22_ADDR			(DRR22_ADDR+6)
#define RCR22      			*(ioport volatile unsigned int *)RCR12_ADDR

#define RCR12_ADDR			(DRR22_ADDR+7)
#define RCR12      			*(ioport volatile unsigned int *)RCR22_ADDR

#define XCR22_ADDR			(DRR22_ADDR+8)
#define XCR22      			*(ioport volatile unsigned int *)XCR22_ADDR

#define XCR12_ADDR			(DRR22_ADDR+9)
#define XCR12      			*(ioport volatile unsigned int *)XCR12_ADDR

#define SRGR22_ADDR			(DRR22_ADDR+10)
#define SRGR22      		*(ioport volatile unsigned int *)SRGR22_ADDR

#define SRGR12_ADDR			(DRR22_ADDR+11)
#define SRGR12      		*(ioport volatile unsigned int *)SRGR12_ADDR

#define MCR22_ADDR			(DRR22_ADDR+12)
#define MCR22      			*(ioport volatile unsigned int *)MCR22_ADDR

#define MCR12_ADDR			(DRR22_ADDR+13)
#define MCR12      			*(ioport volatile unsigned int *)MCR12_ADDR

#define RCERA2_ADDR			(DRR22_ADDR+14)
#define RCERA2     			*(ioport volatile unsigned int *)RCERA2_ADDR

#define RCERB2_ADDR			(DRR22_ADDR+15)
#define RCERB2     			*(ioport volatile unsigned int *)RCERB2_ADDR

#define XCERA2_ADDR			(DRR22_ADDR+16)
#define XCERA2     			*(ioport volatile unsigned int *)XCERA2_ADDR

#define XCERB2_ADDR			(DRR22_ADDR+17)
#define XCERB2     			*(ioport volatile unsigned int *)XCERB2_ADDR

#define PCR2_ADDR			(DRR22_ADDR+18)
#define PCR2      			*(ioport volatile unsigned int *)PCR2_ADDR

#define RCERC2_ADDR			(DRR22_ADDR+19)
#define RCERC2     			*(ioport volatile unsigned int *)RCERC2_ADDR

#define RCERD2_ADDR			(DRR22_ADDR+20)
#define RCERD2     			*(ioport volatile unsigned int *)RCERD2_ADDR

#define XCERC2_ADDR			(DRR22_ADDR+21)
#define XCERC2     			*(ioport volatile unsigned int *)XCERC2_ADDR

#define XCERD2_ADDR			(DRR22_ADDR+22)
#define XCERD2     			*(ioport volatile unsigned int *)XCERD2_ADDR

#define RCERE2_ADDR			(DRR22_ADDR+23)
#define RCERE2     			*(ioport volatile unsigned int *)RCERE2_ADDR

#define RCERF2_ADDR			(DRR22_ADDR+24)
#define RCERF2     			*(ioport volatile unsigned int *)RCERF2_ADDR

#define XCERE2_ADDR			(DRR22_ADDR+25)
#define XCERE2     			*(ioport volatile unsigned int *)XCERE2_ADDR

#define XCERF2_ADDR			(DRR22_ADDR+26)
#define XCERF2     			*(ioport volatile unsigned int *)XCERF2_ADDR

#define RCERG2_ADDR			(DRR22_ADDR+27)
#define RCERG2     			*(ioport volatile unsigned int *)RCERG2_ADDR

#define RCERH2_ADDR			(DRR22_ADDR+28)
#define RCERH2    			*(ioport volatile unsigned int *)RCERH2_ADDR

#define XCERG2_ADDR			(DRR22_ADDR+29)
#define XCERG2     			*(ioport volatile unsigned int *)XCERG2_ADDR

#define XCERH2_ADDR			(DRR22_ADDR+30)
#define XCERH2     			*(ioport volatile unsigned int *)XCERH2_ADDR
*/

/*********************************************************************/
/* Define bit fields for Serial Port Control Registers 1 and 2       */
/*********************************************************************/
#define DLB				15
#define DLB_SZ			1

#define RJUST			13
#define RJUST_SZ	    2

#define CLKSTP			11
#define CLKSTP_SZ	    2

#define DXENA			7
#define DXENA_SZ	    1

#define ABIS			6
#define ABIS_SZ			1

#define RINTM			4
#define RINTM_SZ	    2

#define RSYNCERR	    3
#define RSYNCERR_SZ		1

#define RFULL			2
#define RFULL_SZ	    1

#define RRDY 			1
#define RRDY_SZ			1

#define RRST			0
#define RRST_SZ			1

#define MCBSP_FREE		9
#define MCBSP_FREE_SZ	1

#define SOFT			8
#define SOFT_SZ			1

#define FRST			7
#define FRST_SZ			1

#define GRST			6
#define GRST_SZ			1

#define XINTM			4
#define XINTM_SZ	    2

#define XSYNCERR	    3
#define XSYNCERR_SZ		1

#define XEMPTY			2
#define XEMPTY_SZ	    1

#define XRDY			1
#define XRDY_SZ			1

#define XRST			0
#define XRST_SZ 	    1

/*********************************************************************/
/* Define bit fields for Receive Control Registers 1 and 2           */
/*********************************************************************/
#define RFRLEN1			8
#define RFRLEN1_SZ		7

#define RWDLEN1			5
#define RWDLEN1_SZ		3

#define RPHASE			15
#define RPHASE_SZ	    1

#define RFRLEN2			8
#define RFRLEN2_SZ		7

#define RWDLEN2			5
#define RWDLEN2_SZ		3

#define RCOMPAND	    3
#define RCOMPAND_SZ		2

#define RFIG			2
#define RFIG_SZ			1

#define RDATDLY			0
#define RDATDLY_SZ		2

/*********************************************************************/
/* Define bit fields for Transmit Control Registers 1 and 2          */
/*********************************************************************/
#define XFRLEN1			8
#define XFRLEN1_SZ		7

#define XWDLEN1			5
#define XWDLEN1_SZ		2

#define XPHASE			15
#define XPHASE_SZ	    1

#define XFRLEN2			8
#define XFRLEN2_SZ		7

#define XWDLEN2			5
#define XWDLEN2_SZ		3

#define XCOMPAND	    3
#define XCOMPAND_SZ		2

#define XFIG			2
#define XFIG_SZ  	    1

#define XDATDLY			0
#define XDATDLY_SZ      2

/*********************************************************************/
/* Define bit fields for Sample Rate Generator Registers 1 and 2     */
/*********************************************************************/
#define FWID			8
#define FWID_SZ			8

#define CLKGDV			0
#define CLKGDV_SZ	    8

#define GSYNC			15
#define GSYNC_SZ	    1

#define CLKSP			14 
#define CLKSP_SZ	    1

#define CLKSM			13 
#define CLKSM_SZ	    1

#define FSGM			12 
#define FSGM_SZ			1

#define FPER			0
#define FPER_SZ			12

/*********************************************************************/
/* Define bit fields for Multi-Channel Control Registers 1 and 2     */
/*********************************************************************/
#define RMCME			9
#define RMCME_SZ	    1

#define RPBBLK			7
#define RPBBLK_SZ	    2

#define RPABLK			5
#define RPABLK_SZ	    2

#define RCBLK			2
#define RCBLK_SZ	    3

#define RMCM			0
#define RMCM_SZ			1

#define XMCME			9
#define XMCME_SZ	    1

#define XPBBLK			7
#define XPBBLK_SZ	    2

#define XPABLK			5
#define XPABLK_SZ	    2

#define XCBLK			2
#define XCBLK_SZ	    3

#define XMCM			0
#define XMCM_SZ			2

/***********************************************************************/
/* Define bit fields for Receive Channel Enable Register Partition A-H */
/***********************************************************************/
#define RCE15			15
#define RCE15_SZ	    1

#define RCE14			14
#define RCE14_SZ	    1

#define RCE13			13 
#define RCE13_SZ	    1

#define RCE12			12 
#define RCE12_SZ	    1
   
#define RCE11			11 
#define RCE11_SZ	    1

#define RCE10			10
#define RCE10_SZ	    1

#define RCE9			9
#define RCE9_SZ			1

#define RCE8			8
#define RCE8_SZ			1

#define RCE7			7
#define RCE7_SZ			1

#define RCE6			6
#define RCE6_SZ			1

#define RCE5			5
#define RCE5_SZ			1

#define RCE4			4
#define RCE4_SZ			1

#define RCE3			3
#define RCE3_SZ			1

#define RCE2			2
#define RCE2_SZ			1

#define RCE1			1
#define RCE1_SZ			1

#define RCE0			0
#define RCE0_SZ			1

/*********************************************************************/
/* Define bit fields for Transmit Channel Enable Register Partition A*/
/*********************************************************************/
#define XCE15			15
#define XCE15_SZ	    1

#define XCE14			14
#define XCE14_SZ	    1

#define XCE13			13 
#define XCE13_SZ	    1

#define XCE12			12 
#define XCE12_SZ	    1

#define XCE11			11 
#define XCE11_SZ	    1

#define XCE10			10
#define XCE10_SZ	    1

#define XCE9			9
#define XCE9_SZ			1

#define XCE8			8
#define XCE8_SZ			1