intr.h

Real-Time Digital Signal Processing Implementations, Applications, and Experiments with the TMS320C

/******************************************************************/
/* intr.h                                                         */
/* Copyright (c) Texas Instruments , Incorporated  1997           */
/******************************************************************/
#ifndef _INTR55X_H_
#define _INTR55X_H_

#include "regs55x.h"

typedef void (*ISRFUNC)(void);

/******************************************************************/
/* Define all macros needed to enable/disable interrupts, set     */
/* interrupt vectors, allocate space for interrupt vectors and    */
/* set interrupt vector pointer.                                  */
/******************************************************************/
extern ISRFUNC isr_jump_table[]; //Array of ISR pointers 

/******************************************************************/
/* Define Interrupt Flag and Interrupt Mask Registers             */
/******************************************************************/
#define IER0_ADDR		0x0000 
#define IER0	*(volatile unsigned int*)IER0_ADDR

#define IFR0_ADDR		0x0001
#define IFR0	*(volatile unsigned int*)IFR0_ADDR

#define IER1_ADDR		0x0045
#define IER1	*(volatile unsigned int*)IER1_ADDR

#define IFR1_ADDR		0x0046
#define IFR1	*(volatile unsigned int*)IFR1_ADDR

#define IVPD_ADDR		0x0049
#define IVPD	*(volatile unsigned int*)IVPD_ADDR

#define IVPH_ADDR		0x004a
#define IVPH	*(volatile unsigned int*)IVPH_ADDR

/******************************************************************/
/* Define interrupt FLAG numbers                                  */
/******************************************************************/
//IFR0, IER0
#define INT0		 2
#define INT2		 3
#define TINT0		 4
#define RINT0		 5
#define RINT1		 6
#define XINT1		 7
#define DMAC1	   	 9
#define HINT		 10
#define INT3		 11
#define RINT2		 12
#define XINT2		 13
#define DMAC4		 14
#define DMAC5		 15

//IFR1, IER1
#define INT1		 0
#define XINT0		 1
#define DMAC0		 2
#define INT4		 3
#define DMAC2 		 4
#define DMAC3		 5
#define TINT1		 6
#define INT5		 7

/******************************************************************/
/* Define interrupt trap numbers                                  */
/******************************************************************/
#define RS_TRAP			0
#define NMI_TRAP		1
#define INT0_TRAP		2
#define INT2_TRAP		3
#define TINT0_TRAP	    4
#define RINT0_TRAP		5
#define RINT1_TRAP		6
#define XINT1_TRAP		7

#define DMAC1_TRAP		9
#define HPINT_TRAP		10
#define INT3_TRAP		11
#define RINT2_TRAP		12
#define XINT2_TRAP		13
#define DMAC4_TRAP		14
#define DMAC5_TRAP		15
#define INT1_TRAP		16
#define XINT0_TRAP		17
#define DMAC0_TRAP		18
#define INT4_TRAP		19
#define DMAC2_TRAP		20
#define DMAC3_TRAP		21
#define TINT1_TRAP	    22
#define INT5_TRAP		23
#define BERR_TRAP		24
#define DLOG_TRAP		25
#define RTOS_TRAP		26

//Soft interrupts
#define SINT0_TRAP		0
#define SINT1_TRAP		1
#define SINT2_TRAP		2
#define SINT3_TRAP		3
#define SINT4_TRAP		4
#define SINT5_TRAP		5
#define SINT6_TRAP		6
#define SINT7_TRAP		7
#define SINT8_TRAP		8
#define SINT9_TRAP		9
#define SINT10_TRAP		10
#define SINT11_TRAP		11
#define SINT12_TRAP		12
#define SINT13_TRAP		13
#define SINT14_TRAP		14
#define SINT15_TRAP		15
#define SINT16_TRAP		16
#define SINT17_TRAP		17
#define SINT18_TRAP		18
#define SINT19_TRAP		19
#define SINT20_TRAP		20
#define SINT21_TRAP		21
#define SINT22_TRAP		22
#define SINT23_TRAP		23
#define SINT24_TRAP		24
#define SINT25_TRAP		25
#define SINT26_TRAP		26
#define SINT27_TRAP		27
#define SINT28_TRAP		28
#define SINT29_TRAP		29
#define SINT30_TRAP		30
#define SINT31_TRAP		31

/******************************************************************/
/* Interrupt Vectors											  */
/******************************************************************/
#define BASE_VEC_ADR    0x80

#define RESET_VEC		0x00
#define NMI_VEC			0x08
#define INT0_VEC		0x10
#define INT2_VEC		0x18
#define TINT0_VEC		0x20
#define RINT0_VEC		0x28
#define RINT1_VEC		0x30
#define XINT1_VEC		0x38

#define DMAC1_VEC		0x48
#define HINT_VEC		0x50
#define INT3_VEC		0x58
#define RINT2_VEC		0x60
#define XINT2_VEC		0x68
#define DMAC4_VEC		0x70
#define DMAC5_VEC		0x78
#define INT1_VEC		0x80
#define XINT0_VEC		0x88
#define DMAC0_VEC		0x90
#define INT4_VEC		0x98
#define DMAC2_VEC		0xa0
#define DMAC3_VEC		0xa8
#define TINT1_VEC		0xb0
#define INT5_VEC		0xb8
#define BERR_VEC		0xc0
#define DLOG_VEC		0xc8
#define RTOS_VEC		0xd0

#define SINT0_VEC		0x00
#define SINT1_VEC		0x08
#define SINT2_VEC		0x10
#define SINT3_VEC		0x18
#define SINT4_VEC		0x20
#define SINT5_VEC		0x28
#define SINT6_VEC		0x30
#define SINT7_VEC		0x38
#define SINT8_VEC		0x40
#define SINT9_VEC		0x48
#define SINT10_VEC		0x50
#define SINT11_VEC		0x58
#define SINT12_VEC		0x60
#define SINT13_VEC		0x68
#define SINT14_VEC		0x70
#define SINT15_VEC		0x78
#define SINT16_VEC		0x80
#define SINT17_VEC		0x88
#define SINT18_VEC		0x90
#define SINT19_VEC		0x98
#define SINT20_VEC		0xa0
#define SINT21_VEC		0xa8
#define SINT22_VEC		0xb0
#define SINT23_VEC		0xb8
#define SINT24_VEC		0xc0
#define SINT25_VEC		0xc8
#define SINT26_VEC		0xd0
#define SINT27_VEC		0xd8
#define SINT28_VEC		0xe0
#define SINT29_VEC		0xe8
#define SINT30_VEC		0xf0
#define SINT31_VEC		0xf8



/******************************************************************/
/* INTR_ENABLE - enables all masked interrupts by resetting INTM  */
/*               bit in Status Register 1                         */
/******************************************************************/
#if 1 // Mnemonic for CGTools 1.82 and later.
#define INTR_GLOBAL_ENABLE \
        asm("\tBCLR #st1_intm, st1_55"); \
        asm("\tNOP"); \
        asm("\tNOP"); \
        asm("\tNOP"); \
        asm("\tNOP"); \
        asm("\tNOP"); \
        asm("\tNOP");
#else // Algebraic for CGTools 1.80A and earlier.
#define INTR_GLOBAL_ENABLE \
	asm("\tbit(st1, #st1_intm) = #0"); \
        asm("\tNOP"); \
        asm("\tNOP"); \
        asm("\tNOP"); \
        asm("\tNOP"); \
        asm("\tNOP"); \
        asm("\tNOP");
#endif

/******************************************************************/
/* INTR_DISABLE - disables all masked interrupts by setting INTM  */
/*                bit in Status Register 1                        */
/******************************************************************/
#if 1 // Mnemonic for CGTools 1.82 and later.
#define INTR_GLOBAL_DISABLE \
	asm("\tBSET #st1_intm, st1_55"); \
        asm("\tNOP"); \
        asm("\tNOP"); \
        asm("\tNOP"); \
        asm("\tNOP"); \
        asm("\tNOP"); \
        asm("\tNOP");
#else // Algebraic for CGTools 1.80A and earlier.
#define INTR_GLOBAL_DISABLE \
	asm("\tbit(st1, #st1_intm) = #1"); \
        asm("\tNOP"); \
        asm("\tNOP"); \
        asm("\tNOP"); \
        asm("\tNOP"); \
        asm("\tNOP"); \
        asm("\tNOP");
#endif   

typedef interrupt void (*Ip)(void);

void hook_interrupt(unsigned int trap, Ip func);

void unhook_interrupt(unsigned int trap);

#endif  //_INTR55X_H_