emif.h

Real-Time Digital Signal Processing Implementations, Applications, and Experiments with the TMS320C

/******************************************************************************/
/*  EMIF.H - TMS320C6x Peripheral Support Library EMIF Support                */
/*                                                                            */
/*     This file provides the header for the DSP's EMIF support.              */
/*                                                                            */
/*  MACRO FUNCTIONS:                                                          */
/*    SDRAM_REFRESH_ENABLE()  - Enable SDRAM refresh cycles                   */
/*    SDRAM_REFRESH_DISABLE() - Disable SDRAM refresh cycles                  */
/*    SDRAM_REFRESH_PERIOD()  - Assigns refresh period for SDRAM              */
/*    SDRAM_INIT()            - Perform initialization sequence for SDRAM     */
/*    EMIF_GET_MAP_MODE()     - Return value of MAP bit in EMIF global ctrl   */
/*                                                                            */
/*  FUNCTIONS:                                                                */
/*    emif_init()           - Sets all EMIF registers to parameter values     */
/*                                                                            */
/*    DATE                              DESCRIPTION                           */
/*   -------   -------------------------------------------------------------  */
/*                                                                            */
/******************************************************************************/
#ifndef _EMIF55X_H_
#define _EMIF55X_H_

#include "regs55x.h"

/******************************************************************************/
/* EMIF REGISTERS                                                             */
/******************************************************************************/
#define EMIF_GCTRL_ADDR         0x0800
#define EMIF_GRST_ADDR          0x0801
#define EMIF_BE_ADDR			0x0802

#define EMIF_CE0_CTRL1_ADDR     0x0803
#define EMIF_CE0_CTRL2_ADDR     0x0804
#define EMIF_CE0_CTRL3_ADDR     0x0805

#define EMIF_CE1_CTRL1_ADDR     0x0806
#define EMIF_CE1_CTRL2_ADDR     0x0807
#define EMIF_CE1_CTRL3_ADDR     0x0808

#define EMIF_CE2_CTRL1_ADDR     0x0809
#define EMIF_CE2_CTRL2_ADDR     0x080a
#define EMIF_CE2_CTRL3_ADDR     0x080b

#define EMIF_CE3_CTRL1_ADDR     0x080c
#define EMIF_CE3_CTRL2_ADDR     0x080d
#define EMIF_CE3_CTRL3_ADDR     0x080e

#define EMIF_SDRAM_CTRL1_ADDR   0x080f
#define EMIF_SDRAM_PER_ADDR     0x0810
#define EMIF_SDRAM_CNTR_ADDR    0x0811
#define EMIF_SDRAM_INIT_ADDR    0x0812
#define EMIF_SDRAM_CTRL2_ADDR   0x0813


#define EMIF_GCTRL          (*(ioport volatile unsigned int *)EMIF_GCTRL_ADDR)
#define EMIF_GRST           (*(ioport volatile unsigned int *)EMIF_GRST_ADDR)
#define EMIF_BE             (*(ioport volatile unsigned int *)EMIF_BE_ADDR)

#define EMIF_CE0_CTRL1      (*(ioport volatile unsigned int *)EMIF_CE0_CTRL1_ADDR)
#define EMIF_CE0_CTRL2      (*(ioport volatile unsigned int *)EMIF_CE0_CTRL2_ADDR)
#define EMIF_CE0_CTRL3      (*(ioport volatile unsigned int *)EMIF_CE0_CTRL3_ADDR)

#define EMIF_CE1_CTRL1      (*(ioport volatile unsigned int *)EMIF_CE1_CTRL1_ADDR)
#define EMIF_CE1_CTRL2      (*(ioport volatile unsigned int *)EMIF_CE1_CTRL2_ADDR)
#define EMIF_CE1_CTRL3      (*(ioport volatile unsigned int *)EMIF_CE1_CTRL3_ADDR)

#define EMIF_CE2_CTRL1      (*(ioport volatile unsigned int *)EMIF_CE2_CTRL1_ADDR)
#define EMIF_CE2_CTRL2      (*(ioport volatile unsigned int *)EMIF_CE2_CTRL2_ADDR)
#define EMIF_CE2_CTRL3      (*(ioport volatile unsigned int *)EMIF_CE2_CTRL3_ADDR)

#define EMIF_CE3_CTRL1      (*(ioport volatile unsigned int *)EMIF_CE3_CTRL1_ADDR)
#define EMIF_CE3_CTRL2      (*(ioport volatile unsigned int *)EMIF_CE3_CTRL2_ADDR)
#define EMIF_CE3_CTRL3      (*(ioport volatile unsigned int *)EMIF_CE3_CTRL3_ADDR)


#define EMIF_SDRAM_CTRL1    (*(ioport volatile unsigned int *)EMIF_SDRAM_CTRL1_ADDR)
#define EMIF_SDRAM_CTRL2    (*(ioport volatile unsigned int *)EMIF_SDRAM_CTRL2_ADDR)
#define EMIF_SDRAM_PER      (*(ioport volatile unsigned int *)EMIF_SDRAM_PER_ADDR)
#define EMIF_SDRAM_CNTR     (*(ioport volatile unsigned int *)EMIF_SDRAM_CNTR_ADDR)
#define EMIF_SDRAM_INIT     (*(ioport volatile unsigned int *)EMIF_SDRAM_INIT_ADDR)

//EMIF Global Control Register Bits
#define NOHOLD             0
#define HOLDA              1
#define HOLD               2
#define ARDY               3
#define MEMCEN             5
#define WPE                7
#define MEMFREQ            9
#define MEMFREQ_SZ         2

//EMIF Bus Error Status Register Bits
#define PBUS               0
#define CBUS               2
#define DBUS               3
#define EBUS               4
#define FBUS               5
#define DMA                6
#define CE0                7
#define CE1                8
#define CE2                9
#define CE3                10
#define TIME               12


//EMIF CE0/1/2/3 Control Register 1 Bits
#define READ_HOLD          0
#define READ_HOLD_SZ       2

#define READ_STROBE        2
#define READ_STROBE_SZ     6

#define READ_SETUP         8
#define READ_SETUP_SZ      4

#define MTYPE              12
#define MTYPE_SZ           3

//EMIF CE0/1/2/3 Control Register 2 Bits
#define WRITE_HOLD         0
#define WRITE_HOLD_SZ      2

#define WRITE_STROBE       2
#define WRITE_STROBE_SZ    6

#define WRITE_SETUP        8
#define WRITE_SETUP_SZ     4

#define EXT_HOLD_WRITE     12
#define EXT_HOLD_WRITE_SZ  2

#define EXT_HOLD_READ      14
#define EXT_HOLD_READ_SZ   2

//EMIF CE0/1/2/3 Control Register 3 Bits
#define TIMEOUT            0
#define TIMEOUT_SZ         8


//EMIF SDRAM Control Register 1 Bits
#define TRP                0
#define TRP_SZ             4

#define TRCD               4
#define TRCD_SZ            4

#define RFEN               8

#define SDWID              9

#define SDSIZE             10

#define TRC                11
#define TRC_SZ             5

//EMIF SDRAM Control Register 2 Bits
#define TACTV2ACTV         0
#define TACTV2ACTV_SZ      4

#define TRAS               4
#define TRAS_SZ            4

#define TMRD               8
#define TMRD_SZ            2

//EMIF SDRAM Timing Register Bits
#define PERIOD             0
#define PERIOD_SZ         12

#define COUNTER           12
#define COUNTER_SZ        12

//EMIF Global Control Register Bitfield Values

//EMIF CE Space Control Register Bitfield Values
#define MTYPE_8ASYNC        0x00     //8 bit asynchronous interface        
#define MTYPE_16ASYNC       0x01     //16 bit asynchronous interface        
#define MTYPE_32ASYNC       0x02     //32 bit asynchronous interface        
#define MTYPE_32SDRAM       0x03     //32 bit SDRAM                         
#define MTYPE_32SBSRAM      0x04     //32 bit SBSRAM                        

//---------------------------------------------------------------------------
// MACRO FUNCTIONS                                                           
//---------------------------------------------------------------------------

#define SDRAM_REFRESH_ENABLE() \
	EMIF_SDRAM_CTRL1 |= (1<<RFEN)

#define SDRAM_REFRESH_DISABLE() \
	EMIF_SDRAM_CTRL1 &= ~(1<<RFEN)

#define SDRAM_REFRESH_PERIOD(val) \
	EMIF_SDRAM_PER &= (~CREATE_FIELD(PERIOD,PERIOD_SZ)) | TRUNCATE(val, PERIOD, PERIOD_SZ;

//---------------------------------------------------------------------------
// STRUCTURES                                                           
//---------------------------------------------------------------------------
typedef struct _EmifSpaceCtrl
{ 
    unsigned int ctrl1;
    unsigned int ctrl2;
    unsigned int ctrl3;
} EmifSpaceCtrl, *PEmifSpaceCtrl;

typedef struct _EmifSdramCtrl
{ 
    unsigned int ctrl1;
    unsigned int ctrl2;
    unsigned int per;
    unsigned int cntr;
    unsigned int init;
} EmifSdramCtrl, *PEmifSdramCtrl;

//---------------------------------------------------------------------------
// FUNCTIONS PROTOTYPES
//---------------------------------------------------------------------------
void emif_init(unsigned int g_ctrl,
						   PEmifSpaceCtrl ce0_ctrl,
						   PEmifSpaceCtrl ce1_ctrl,
						   PEmifSpaceCtrl ce2_ctrl,
						   PEmifSpaceCtrl ce3_ctrl,
						   PEmifSdramCtrl sdram_ctrl);

void emif_reset();

#endif  //_EMIF55X_H_