📄 dma55x.h
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//DMCCR
#define DMSYNC_OFF 0x00 //No event synchronized
#define DMSYNC_REVT0 0x01 //McBsp 0 Rx Event
#define DMSYNC_XEVT0 0x02 //McBsp 0 Tx Event
#define DMSYNC_REVTA0 0x03 //McBsp 0 Rx EventA
#define DMSYNC_XEVTA0 0x04 //McBsp 0 Tx EventA
#define DMSYNC_REVT1 0x05 //McBsp 1 Rx Event
#define DMSYNC_XEVT1 0x06 //McBsp 1 Tx Event
#define DMSYNC_REVTA1 0x07 //McBsp 1 Rx EventA
#define DMSYNC_XEVTA1 0x08 //McBsp 1 Tx EventA
#define DMSYNC_REVT2 0x09 //McBsp 2 Rx Event
#define DMSYNC_XEVT2 0x0a //McBsp 2 Tx Event
#define DMSYNC_REVTA2 0x0b //McBsp 2 Rx EventA
#define DMSYNC_XEVTA2 0x0c //McBsp 2 Tx EvenA
#define DMSYNC_TIMER1 0x0d //Timer 1 Event
#define DMSYNC_TIMER2 0x0e //Timer 2 Event
#define DMSYNC_EXT0 0x0f //External Ineterrupt 0
#define DMSYNC_EXT1 0x10 //External Ineterrupt 0
#define DMSYNC_EXT2 0x11 //External Ineterrupt 0
#define DMSYNC_EXT3 0x12 //External Ineterrupt 0
#define DMSYNC_EXT4 0x13 //External Ineterrupt 0
#define DMSYNC_EXT5 0x14 //External Ineterrupt 0
#define DM_FS_ON 0x00 //Double word transfer mode is disabled
#define DM_FS_OFF 0x01 //Double word transfer mode is enabled
#define DM_PRIO_HIGH 0x01 //Channel has high priority
#define DM_PRIO_LOW 0x00 //Channel has low priority
#define DM_ENABLE 0x01 //Start transfer
#define DM_DISABLE 0x00 //Disable transfer
#define DM_AUTOINIT_ON 0x01 //Auto-initialization enabled
#define DM_AUTOINIT_OFF 0x00 //Auto-initialization enabled disabled
#define DM_REPEAT_ON 0x01 //Auto-initialization regardless of DM_END_PROG
#define DM_REPEAT_OFF 0x00 //Auto-initialization only if DM_END_PROG=1
#define DM_FIFO_FLUSH_ON 0x01 //FIFO is flushed
#define DM_FIFO_FLUSH_OFF 0x00 //No flushing occurs
#define DM_END_PROG_ON 0x01 //Allows the ch to re-init itself if DM_AUTOINIT=1
#define DM_END_PROG_OFF 0x00 //Delays the ch re-init if DM_AUTOINIT=1
#define DM_NOMOD 0x00 //Constant address
#define DM_POST_INCR 0x01 //Increment address
#define DM_INDX_INCR 0x02 //Increment address by element index
#define DM_FRM_INDX_INCR 0x03 //Increment address by element and frame index
//DMCICR
#define DMINTR_TIMEOUT (1<<DM_TIMEOUT) //Interrupt if timeout
#define DMINTR_DROP (1<<DM_DROP) //Interrupt if timeout
#define DMINTR_1STHALF (1<<DM_1STHALF) //Interrupt if timeout
#define DMINTR_FRAME (1<<DM_FRAME) //Interrupt if timeout
#define DMINTR_LAST (1<<DM_LAST) //Interrupt if timeout
#define DMINTR_BLOCK (1<<DM_BLOCK) //Interrupt if timeout
//DMA channels
#define DMCH0 0x00 // DMA Channel 0
#define DMCH1 0x01 // DMA Channel 1
#define DMCH2 0x02 // DMA Channel 2
#define DMCH3 0x03 // DMA Channel 3
#define DMCH4 0x04 // DMA Channel 4
#define DMCH5 0x05 // DMA Channel 5
/****************************************************************************/
/* MACRO DEFINITIONS */
/****************************************************************************/
/****************************************************************************/
/* DMA_ENABLE - enable selected DMA ch */
/****************************************************************************/
#define DMA_ENABLE(ch) \
DMCCR(ch) = DMCCR(ch) | (1<<DM_EN)
/****************************************************************************/
/* DMA_DISABLE - disable selected DMA ch */
/****************************************************************************/
#define DMA_DISABLE(ch) \
DMCCR(ch) &= ~(1<<DM_EN)
/****************************************************************************/
/* DMA_AUTO_ENABLE - enable selected DMA ch with auto-init */
/****************************************************************************/
#define DMA_AUTO_ENABLE(ch) \
{DMCCR_ADDR(ch) |= ((1<<DM_AUTOINIT) | (1<<DM_END_PROG));\
DMA_ENABLE(ch);}
/****************************************************************************/
/* DMA_FREE_RUNNING - enable DMA free running */
/****************************************************************************/
#define DMA_FREE_RUNNING \
DMCCR(ch) |= (1<<DM_FREE)
/****************************************************************************/
/* DMA_NO_FREE_RUNNING - disable DMA free running */
/****************************************************************************/
#define DMA_NO_FREE_RUNNING \
DMCCR(ch) &= ~(1<<DM_FREE)
/****************************************************************************/
/* DMA_FRAMECOUNT - set number of frames in multi-frame transfer */
/****************************************************************************/
#define DMA_FRAME_COUNT(ch, value) \
DMCFN(ch) = value
/****************************************************************************/
/* DMA_FRAMECOUNT - set number of frames in multi-frame transfer */
/****************************************************************************/
#define DMA_ELEMENT_COUNT(ch, value) \
DMCEN(ch) = value
/****************************************************************************/
/* DMA_FRAME_INDEX - set frame index in multi-frame transfer */
/****************************************************************************/
#define DMA_FRAME_INDEX(ch, value) \
DMCFI(ch) = value
/****************************************************************************/
/* DMA_ELEMENT_INDEX - set element index */
/****************************************************************************/
#define DMA_ELEMENT_INDEX(ch, value) \
DMCEI_ADDR(ch) = value
/******************************************************************/
/* Structure definitions */
/******************************************************************/
typedef struct _Dma55xConfig
{
int ch; //DMA channel
unsigned int csdp; //DMCSDP
unsigned int ccr; //DMCCR
unsigned int cicr; //CICR
unsigned int srcl; //src address (LSW)
unsigned int srch; //src address (MSW)
unsigned int dstl; //dst address (LSW)
unsigned int dsth; //src address (MSW)
unsigned int elem; //element count
unsigned int frame; //frame count
unsigned int framei; //frame index in multi-frame transfer
unsigned int elemi; //element index
} Dma55xConfig, *PDma55xConfig;
/****************************************************************************/
/* FUNCTION DEFINITIONS */
/****************************************************************************/
/****************************************************************************/
/* dma_init - Initialize ch specific control registers. */
/* */
/* This function is responsible for setting the DMA control registers, */
/* source address, destination address and the corresponding pages */
/* transfer count for the specified DMA ch. */
/* */
/****************************************************************************/
void dma_init(PDma55xConfig pDma);
/****************************************************************************/
/* dma_global_init - Initialize global control registers. */
/* */
/* This function is responsible for setting the DMA global control */
/* register */
/****************************************************************************/
void dma_global_init(unsigned int gcr);
/*****************************************************************************/
/* dma_reset - Reset DMA ch. */
/* */
/* This function resets the specified DMA ch by initializing */
/* ch control registers to their default values */
/* */
/*****************************************************************************/
void dma_reset(int ch);
/*****************************************************************************/
/* dma_reset_all - Reset all DMA channels. */
/* */
/* This function resets all DMA channels by initializing */
/* ch control registers to their default values */
/* */
/*****************************************************************************/
void dma_reset_all(void);
#endif //_DMA55X_H_
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