dma55x.h

Real-Time Digital Signal Processing Implementations, Applications, and Experiments with the TMS320C

/******************************************************************************/
/*  DMA55XX.H - DMA55xx routines header file.                                 */
/*                                                                            */
/*     This module provides the devlib implementation for the DMAC            */
/*     on the TMS320C55XX DSP.                                                */
/*                                                                            */
/*  MACRO FUNCTIONS:                                                          */
/*     DMA_ENABLE 		- enable selected DMA ch                              */                      
/*     DMA_DISABLE 		- disable selected DMA ch                             */
/*     DMA_AUTO_ENABLE 		- enable selected DMA ch with auto-init           */
/*     DMA_FREE_RUNNING 	- enable DMA free running                         */
/*     DMA_NO_FREE_RUNNING 	- disable DMA free running                        */
/*     DMA_FRAMECOUNT 		- set number of frames in multi-frame transfer    */
/*     DMA_INTMASK_ENABLE 	- enable DMA interrupt                            */
/*     DMA_INTMASK_DISABLE 	- disable DMA interrupt                           */
/*     DMA_DMS_SELECT 		- set Source Space Select                         */
/*     DMA_DMD_SELECT 		- set Destination Space Select                    */
/*                                                                            */
/*  FUNCTIONS:                                                                */
/*     dma_init 		 -  Initialize ch specific control registers          */
/*     dma_global_init() - Initialize global control registers.               */
/*     dma_reset_all()       - Resets indicated DMA ch                        */
/*                                                                            */
/*                                                                            */
/*  AUTHOR:                                                                   */
/*     Stefan Haas                                                            */
/*                                                                            */
/*  REVISION HISTORY:                                                         */
/*                                                                            */
/*    DATE       AUTHOR                       DESCRIPTION                     */
/*   -------   -------------      ------------------------------------------  */
/*   13OCT98   St Haas            Original.                                   */
/*                                                                            */
/******************************************************************************/
#ifndef _DMA55X_H_
#define _DMA55X_H_

#include "regs55x.h"

/******************************************************************************/
/* Register Definition for 55x DMA      									  */
/******************************************************************************/
#define DMGCR_ADDR			0x0e00
#define DMGCR				*(ioport volatile unsigned int *)DMGCR_ADDR

#define DMCSDP_ADDR(port)	(0x0c00+(port * 0x20))
#define DMCSDP(port)    	*(ioport volatile unsigned int *)DMCSDP_ADDR(port)

#define DMCCR_ADDR(port)    (DMCSDP_ADDR(port)+1)
#define DMCCR(port)    		*(ioport volatile unsigned int *)DMCCR_ADDR(port)

#define DMCICR_ADDR(port)   (DMCCR_ADDR(port)+1)
#define DMCICR(port)    	*(ioport volatile unsigned int *)DMCICR_ADDR(port)

#define DMCSR_ADDR(port)    (DMCSDP_ADDR(port)+3)
#define DMCSR(port)    		*(ioport volatile unsigned int *)DMCSR_ADDR(port)

#define DMCSSAL_ADDR(port)  (DMCSDP_ADDR(port)+4)
#define DMCSSAL(port)    	*(ioport volatile unsigned int *)DMCSSAL_ADDR(port)

#define DMCSSAU_ADDR(port)  (DMCSDP_ADDR(port)+5)
#define DMCSSAU(port)    	*(ioport volatile unsigned int *)DMCSSAU_ADDR(port)

#define DMCDSAL_ADDR(port)  (DMCSDP_ADDR(port)+6)
#define DMCDSAL(port)    	*(ioport volatile unsigned int *)DMCDSAL_ADDR(port)

#define DMCDSAU_ADDR(port)  (DMCSDP_ADDR(port)+7)
#define DMCDSAU(port)    	*(ioport volatile unsigned int *)DMCDSAU_ADDR(port)

#define DMCEN_ADDR(port)    (DMCSDP_ADDR(port)+8)
#define DMCEN(port)    		*(ioport volatile unsigned int *)DMCEN_ADDR(port)

#define DMCFN_ADDR(port)    (DMCSDP_ADDR(port)+9)
#define DMCFN(port)    		*(ioport volatile unsigned int *)DMCFN_ADDR(port)

#define DMCFI_ADDR(port)    (DMCSDP_ADDR(port)+0xa)
#define DMCFI(port)    		*(ioport volatile unsigned int *)DMCFI_ADDR(port)

#define DMCEI_ADDR(port)    (DMCSDP_ADDR(port)+0xb)
#define DMCEI(port)    		*(ioport volatile unsigned int *)DMCEI_ADDR(port)

/******************************************************************************/
/*  DMA   Registers, Bits, Bitfields										  */
/******************************************************************************/
//DMGCR
#define DM_EHPI_PRIO		0
#define DM_EHPI_PRIO_SZ		1

#define DM_EHPI_EXCL		1
#define DM_EHPI_EXCL_SZ		1

#define DM_FREE				2
#define DM_FREE_SZ			1

//DMCSDP
#define DM_DATA_TYPE		0
#define DM_DATA_TYPE_SZ		2

#define DM_SRC				2
#define DM_SRC_SZ			4

#define DM_SRC_PACK			6
#define DM_SRC_PACK_SZ		1

#define DM_SRC_BEN			7
#define DM_SRC_BEN_SZ		2

#define DM_DST				9
#define DM_DST_SZ			4

#define DM_DST_PACK			13
#define DM_DST_PACK_SZ		1

#define DM_DST_BEN			14
#define DM_DST_BEN_SZ		2

//DMCCR
#define DM_SYNC				0
#define DM_SYNC_SZ			5

#define DM_FS				5
#define DM_FS_SZ			1

#define DM_PRIO				6
#define DM_PRIO_SZ			1

#define DM_EN				7
#define DM_EN_SZ			1

#define DM_AUTOINIT			8
#define DM_AUTOINIT_SZ		1

#define DM_REPEAT			9
#define DM_REPEAT_SZ		1

#define DM_FIFO_FLUSH		10
#define DM_FIFO_FLUSH_SZ	1

#define DM_END_PROG			11
#define DM_END_PROG_SZ		1

#define DM_SRC_AMODE		12
#define DM_SRC_AMODE_SZ		2

#define DM_DST_AMODE		14
#define DM_DST_AMODE_SZ		2

//DMCICR/DMCSR
#define DM_TIMEOUT			0
#define DM_TIMEOUT_SZ		1

#define DM_DROP				1
#define DM_DROP_SZ			1

#define DM_1STHALF			2
#define DM_1STHALF_SZ		1

#define DM_FRAME			3
#define DM_FRAME_SZ			1

#define DM_LAST				4
#define DM_LAST_SZ			1

#define DM_BLOCK			5
#define DM_BLOCK_SZ			1

/******************************************************************************/
/* CONFIGURATION REGISTER BIT and BITFIELD values                   		  */
/******************************************************************************/
//DMGCR
#define DM_EHPI_PRIO_LOW    0x00     //Lowest priority for EHPI DMA ch
#define DM_EHPI_PRIO_HIGH  	0x01     //Highest priority for EHPI DMA ch

#define DM_EXCL_ON			0x00     //EHPI has exclusive on-chip RAM access
#define DM_EXCL_OFF	  		0x01     //EHPI does not have exclusive access

#define DM_FREE_OFF			0x00     //DMA stops after the DMA xfer complete
#define DM_FREE_ON			0x01     //DMA runs free, even if device halted

//DMCSDP
#define DM_DTYPE_8          0x00     //8-bit data
#define DM_DTYPE_16         0x01     //16-bit data
#define DM_DTYPE_32         0x02     //32-bit data

#define DM_SARAM			0x0000   //src/dst port is SARAM
#define DM_DARAM			0x0001   //src/dst port is DARAM
#define DM_EMIF				0x0002   //src/dst port is EMIF
#define DM_RHEA				0x0003   //src/dst port is RHEA

#define DM_PACK_ON			0x01	 //pack data 
#define DM_PACK_OFF			0x00	 //do not pack data 

#define DM_NO_BURST			0x00	 //Single access (no burst)
#define DM_BURST4			0x02	 //burst of 4