clock.c

Real-Time Digital Signal Processing Implementations, Applications, and Experiments with the TMS320C

/******************************************************************************/
/*  clock.c - TMS320C55x Peripheral Support Library clock Support             */
/*                                                                            */
/*     This file provides support for the TMS320C55x DSP's clock              */
/*     configuration   .                                                      */
/*                                                                            */
/*  FUNCTIONS:                                                                */
/*    clock_init() - Sets clock rate to specified value                       */
/******************************************************************************/

/******************************************************************************/
/* INCLUDES                                                                   */
/******************************************************************************/
#include "regs55x.h"

/******************************************************************************/
/* LOCAL DEFINES                                                              */
/******************************************************************************/
#define DIE_ID3_ADDR	0x3803
#define DIE_ID3 		*(ioport volatile unsigned int *)DIE_ID3_ADDR

#define DIE_ID2_ADDR	0x3802
#define DIE_ID2 		*(ioport volatile unsigned int *)DIE_ID2_ADDR

#define PLLENABLE		4
#define PLLENABLE_SZ	1

#define PLLDIV			5
#define PLLDIV_SZ		2

#define PLLMULT			7
#define PLLMULT_SZ		4

#define VCO_ONOFF		11
#define VCO_ONOFF_SZ	1

/******************************************************************************/
/* FILE LOCAL (STATIC) VARIABLES                                              */
/******************************************************************************/

/******************************************************************************/
/* FILE LOCAL (STATIC) PROTOTYPES                                             */
/******************************************************************************/
#pragma CODE_SECTION(DPLL_init, "DRV5510");
#pragma CODE_SECTION(APLL_init, "DRV5510");

void DPLL_init(unsigned int inclk, unsigned int outclk, unsigned int plldiv);
void APLL_init(unsigned int inclk, unsigned int outclk, unsigned int plldiv);

/******************************************************************************/
/* FUNCTIONS                                                                  */
/******************************************************************************/
#pragma CODE_SECTION(clock_init, "DRV5510");

/******************************************************************************/
/* clock_init() -  Initialize clock frequency to specified value              */
/*                                                                            */
/* if pllmult > 1                                                             */
/*		outclk = (pllmult / (plldiv + 1)) * inclk                             */
/*                                                                            */
/* if pllmult < 1                                                             */
/*		outclk = (1 / (plldiv + 1)) * inclk                                   */
/*                                                                            */
/******************************************************************************/
void clock_init(unsigned int inclk, unsigned int outclk, unsigned int plldiv)
{
	unsigned int dieid3, dieid2;
		
	dieid3 = DIE_ID3;
	dieid2 = DIE_ID2;
	
	if ((dieid3 && 0x0001) & (dieid2 && 0x4000))
	{
		/* rev 1.1/1.1a/1.2 Si */
	    APLL_init(inclk, outclk, plldiv);
	}
	else
	{
		/* rev 1.0/1.0a Si */
    	DPLL_init(inclk, outclk, plldiv);
    }
}

/******************************************************************************/
/* DPLL_init() -  Initialize clock frequency to specified value               */
/*                                                                            */
/* if pllmult > 1                                                             */
/*		outclk = (pllmult / (plldiv + 1)) * inclk                             */
/*                                                                            */
/* if pllmult < 1                                                             */
/*		outclk = (1 / (plldiv + 1)) * inclk                                   */
/*                                                                            */
/******************************************************************************/
void DPLL_init(unsigned int inclk, unsigned int outclk, unsigned int plldiv)
{
    unsigned int pllmult = (outclk * (plldiv+1)) / inclk;
            
    // ensure plldiv is only 2 bits
    plldiv &= 0x3u;

	//force into BYPASS mode (b4=0)
    CLKMD = 0;	

	//wait for BYPASS mode to be active
    while (CLKMD & (1<<LOCK));	

	CLKMD = ((1<<IOB)|(pllmult<<PLL_MULT)|(plldiv<<PLL_DIV)|(plldiv<<BYPASS_DIV)|(1<<PLL_ENABLE));
		
	//wait for PLL mode to be active if pllmult > 1
	if (pllmult > 1)
	{
		while (!(CLKMD & (1<<LOCK))); 
	}
}


/******************************************************************************/
/* APLL_init() -  Initialize clock frequency to specified value               */
/*                                                                            */
/* if pllmult > 1                                                             */
/*		outclk = (pllmult / (plldiv + 1)) * inclk                             */
/*                                                                            */
/* if pllmult < 1                                                             */
/*		outclk = (1 / (plldiv + 1)) * inclk                                   */
/*                                                                            */
/******************************************************************************/
void APLL_init(unsigned int inclk, unsigned int outclk, unsigned int plldiv)
{
    unsigned int pllmult = (outclk * (plldiv+1)) / inclk;
    unsigned int aplldiv, apllmult = 0;
            
    // ensure plldiv is only 2 bits
    plldiv &= 0x3u;

	if (pllmult % 2)
	{
		/* odd */
		aplldiv = 0x0003;
		apllmult = pllmult - 1;		
	}
	else
	{
		/* even */
		aplldiv = 0x0002;
		apllmult = (outclk == inclk) ? 0x000F : ((pllmult/2) - 1);
	}
	
	//force into BYPASS mode (b4=0)
    CLKMD = 0;	

	//wait for BYPASS mode to be active
    while (CLKMD & (1<<PLLENABLE));	

	CLKMD = ((1<<VCO_ONOFF)|(apllmult<<PLLMULT)|(aplldiv<<PLLDIV)|(1<<PLLENABLE));
		
	//wait for PLL mode to be active if pllmult > 1
	if (pllmult > 1)
	{
		while (!(CLKMD & (1<<PLLENABLE))); 
	}
}