📄 eeproma.lst
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+1 198 ; EP8GPIFTCH XDATA 0xE6E8 ; EP8 GPIF Transaction Count High
+1 199 ; EP8GPIFTCL XDATA 0xE6E9 ; EP8GPIF Transaction Count Low
E6EA +1 200 EP8GPIFFLGSEL XDATA 0xE6EA ; EP8 GPIF Flag select
E6EB +1 201 EP8GPIFPFSTOP XDATA 0xE6EB ; Stop GPIF EP8 transaction on prog. flag
E6EC +1 202 EP8GPIFTRIG XDATA 0xE6EC ; EP8 FIFO Trigger
E6F0 +1 203 XGPIFSGLDATH XDATA 0xE6F0 ; GPIF Data H (16-bit mode only)
E6F1 +1 204 XGPIFSGLDATLX XDATA 0xE6F1 ; Read/Write GPIF Data L & trigger transac
E6F2 +1 205 XGPIFSGLDATLNOX XDATA 0xE6F2 ; Read GPIF Data L, no transac trigger
E6F3 +1 206 GPIFREADYCFG XDATA 0xE6F3 ; Internal RDY,Sync/Async, RDY5CFG
E6F4 +1 207 GPIFREADYSTAT XDATA 0xE6F4 ; RDY pin states
E6F5 +1 208 GPIFABORT XDATA 0xE6F5 ; Abort GPIF cycles
+1 209
+1 210 ; UDMA
+1 211
E6C6 +1 212 FLOWSTATE XDATA 0xE6C6 ; Defines GPIF flow state
E6C7 +1 213 FLOWLOGIC XDATA 0xE6C7 ; Defines flow/hold decision criteria
E6C8 +1 214 FLOWEQ0CTL XDATA 0xE6C8 ; CTL states during active flow state
E6C9 +1 215 FLOWEQ1CTL XDATA 0xE6C9 ; CTL states during hold flow state
E6CB +1 216 FLOWSTB XDATA 0xE6CB ; CTL/RDY Signal to use as master data strobe
E6CC +1 217 FLOWEDGE XDATA 0xE6CC ; Defines active master strobe edge
E6CD +1 218 FLOWSTBHPERIOD XDATA 0xE6CD ; Half Period of output master strobe
E60C +1 219 GPIFHOLDAMOUNT XDATA 0xE60C ; Data delay shift
E67D +1 220 UDMACRCH XDATA 0xE67D ; CRC Upper byte
E67E +1 221 UDMACRCL XDATA 0xE67E ; CRC Lower byte
E67F +1 222 UDMACRCQUAL XDATA 0xE67F ; UDMA In only, host terminated use only
+1 223
+1 224
+1 225 ; Debug/Test
+1 226
E6F8 +1 227 DBUG XDATA 0xE6F8 ; Debug
E6F9 +1 228 TESTCFG XDATA 0xE6F9 ; Test configuration
E6FA +1 229 USBTEST XDATA 0xE6FA ; USB Test Modes
E6FB +1 230 CT1 XDATA 0xE6FB ; Chirp Test--Override
E6FC +1 231 CT2 XDATA 0xE6FC ; Chirp Test--FSM
E6FD +1 232 CT3 XDATA 0xE6FD ; Chirp Test--Control Signals
E6FE +1 233 CT4 XDATA 0xE6FE ; Chirp Test--Inputs
+1 234
+1 235 ; Endpoint Buffers
+1 236
E740 +1 237 EP0BUF XDATA 0xE740 ; EP0 IN-OUT buffer
E780 +1 238 EP10UTBUF XDATA 0xE780 ; EP1-OUT buffer
E7C0 +1 239 EP1INBUF XDATA 0xE7C0 ; EP1-IN buffer
F000 +1 240 EP2FIFOBUF XDATA 0xF000 ; 512/1024-byte EP2 buffer (IN or OUT)
F400 +1 241 EP4FIFOBUF XDATA 0xF400 ; 512 byte EP4 buffer (IN or OUT)
F800 +1 242 EP6FIFOBUF XDATA 0xF800 ; 512/1024-byte EP6 buffer (IN or OUT)
FC00 +1 243 EP8FIFOBUF XDATA 0xFC00 ; 512 byte EP8 buffer (IN or OUT)
+1 244
+1 245 ;/*-----------------------------------------------------------------------------
+1 246 ; Special Function Registers (SFRs)
+1 247 ; The byte registers and bits defined in the following list are based
+1 248 ; on the Synopsis definition of the 8051 Special Function Registers for EZ-USB.
+1 249 ; If you modify the register definitions below, please regenerate the file
+1 250 ; "ezregs.inc" which includes the same basic information for assembly inclusion.
+1 251 ;-----------------------------------------------------------------------------*/
+1 252
0080 +1 253 IOA DATA 080H
0081 +1 254 SP DATA 081H
0082 +1 255 DPL DATA 082H
A51 MACRO ASSEMBLER EEPROMA 11/07/2006 14:52:11 PAGE 5
0083 +1 256 DPH DATA 083H
0084 +1 257 DPL1 DATA 084H
0085 +1 258 DPH1 DATA 085H
0086 +1 259 DPS DATA 086H
+1 260 ; DPS
0086 +1 261 SEL BIT 086H+0H
0087 +1 262 PCON DATA 087H
+1 263 ; PCON
+1 264 ;IDLE BIT 087H+0H
+1 265 ;STOP BIT 087H+1H
+1 266 ;GF0 BIT 087H+2H
+1 267 ;GF1 BIT 087H+3H
+1 268 ;SMOD0 BIT 087H+7H
0088 +1 269 TCON DATA 088H
+1 270 ; TCON
0088 +1 271 IT0 BIT 088H+0H
0089 +1 272 IE0 BIT 088H+1H
008A +1 273 IT1 BIT 088H+2H
008B +1 274 IE1 BIT 088H+3H
008C +1 275 TR0 BIT 088H+4H
008D +1 276 TF0 BIT 088H+5H
008E +1 277 TR1 BIT 088H+6H
008F +1 278 TF1 BIT 088H+7H
0089 +1 279 TMOD DATA 089H
+1 280 ; TMOD
+1 281 ;M00 BIT 089H+0H
+1 282 ;M10 BIT 089H+1H
+1 283 ;CT0 BIT 089H+2H
+1 284 ;GATE0 BIT 089H+3H
+1 285 ;M01 BIT 089H+4H
+1 286 ;M11 BIT 089H+5H
+1 287 ;CT1 BIT 089H+6H
+1 288 ;GATE1 BIT 089H+7H
008A +1 289 TL0 DATA 08AH
008B +1 290 TL1 DATA 08BH
008C +1 291 TH0 DATA 08CH
008D +1 292 TH1 DATA 08DH
008E +1 293 CKCON DATA 08EH
+1 294 ; CKCON
+1 295 ;MD0 BIT 089H+0H
+1 296 ;MD1 BIT 089H+1H
+1 297 ;MD2 BIT 089H+2H
+1 298 ;T0M BIT 089H+3H
+1 299 ;T1M BIT 089H+4H
+1 300 ;T2M BIT 089H+5H
+1 301 ;SPC_FNC DATA 08FH ; Was WRS in Reg320
+1 302 ; CKCON
+1 303 ;WRS BIT 08FH+0H
0090 +1 304 IOB DATA 090H
0091 +1 305 EXIF DATA 091H ; EXIF Bit Values differ from Reg320
+1 306 ; EXIF
+1 307 ;USBINT BIT 091H+4H
+1 308 ;I2CINT BIT 091H+5H
+1 309 ;IE4 BIT 091H+6H
+1 310 ;IE5 BIT 091H+7H
0092 +1 311 MPAGE DATA 092H
0098 +1 312 SCON0 DATA 098H
+1 313 ; SCON0
0098 +1 314 RI BIT 098H+0H
0099 +1 315 TI BIT 098H+1H
009A +1 316 RB8 BIT 098H+2H
009B +1 317 TB8 BIT 098H+3H
009C +1 318 REN BIT 098H+4H
009D +1 319 SM2 BIT 098H+5H
009E +1 320 SM1 BIT 098H+6H
009F +1 321 SM0 BIT 098H+7H
A51 MACRO ASSEMBLER EEPROMA 11/07/2006 14:52:11 PAGE 6
0099 +1 322 SBUF0 DATA 099H
+1 323
009A +1 324 APTR1H DATA 09AH ; old name
009B +1 325 APTR1L DATA 09BH ; old name
009A +1 326 AUTOPTR1H DATA 09AH
009B +1 327 AUTOPTR1L DATA 09BH
009D +1 328 AUTOPTRH2 DATA 09DH
009E +1 329 AUTOPTRL2 DATA 09EH
00A0 +1 330 IOC DATA 0A0H
00A1 +1 331 INT2CLR DATA 0A1H
00A2 +1 332 INT4CLR DATA 0A2H
+1 333
00A8 +1 334 IE DATA 0A8H
+1 335 ; IE
00A8 +1 336 EX0 BIT 0A8H+0H
00A9 +1 337 ET0 BIT 0A8H+1H
00AA +1 338 EX1 BIT 0A8H+2H
00AB +1 339 ET1 BIT 0A8H+3H
00AC +1 340 ES0 BIT 0A8H+4H
00AD +1 341 ET2 BIT 0A8H+5H
00AE +1 342 ES1 BIT 0A8H+6H
00AF +1 343 EA BIT 0A8H+7H
+1 344
00AA +1 345 EP2468STAT DATA 0AAH
+1 346 ; EP2468STAT
+1 347 ;EP2E BIT 0AAH+0H
+1 348 ;EP2F BIT 0AAH+1H
+1 349 ;EP4E BIT 0AAH+2H
+1 350 ;EP4F BIT 0AAH+3H
+1 351 ;EP6E BIT 0AAH+4H
+1 352 ;EP6F BIT 0AAH+5H
+1 353 ;EP8E BIT 0AAH+6H
+1 354 ;EP8F BIT 0AAH+7H
+1 355
00AB +1 356 EP24FIFOFLGS DATA 0ABH
00AC +1 357 EP68FIFOFLGS DATA 0ACH
00AF +1 358 AUTOPTRSETUP DATA 0AFH
+1 359 ; AUTOPTRSETUP
+1 360 ;EXTACC BIT 0AFH+0H
+1 361 ;APTR1FZ BIT 0AFH+1H
+1 362 ;APTR2FZ BIT 0AFH+2H
+1 363
00B0 +1 364 IOD DATA 0B0H
00B1 +1 365 IOE DATA 0B1H
00B2 +1 366 OEA DATA 0B2H
00B3 +1 367 OEB DATA 0B3H
00B4 +1 368 OEC DATA 0B4H
00B5 +1 369 OED DATA 0B5H
00B6 +1 370 OEE DATA 0B6H
+1 371
00B8 +1 372 IP DATA 0B8H
+1 373 ; IP
00B8 +1 374 PX0 BIT 0B8H+0H
00B9 +1 375 PT0 BIT 0B8H+1H
00BA +1 376 PX1 BIT 0B8H+2H
00BB +1 377 PT1 BIT 0B8H+3H
00BC +1 378 PS0 BIT 0B8H+4H
00BD +1 379 PT2 BIT 0B8H+5H
00BE +1 380 PS1 BIT 0B8H+6H
+1 381
00BA +1 382 EP01STAT DATA 0BAH
00BB +1 383 GPIFTRIG DATA 0BBH
+1 384
00BD +1 385 GPIFSGLDATH DATA 0BDH
00BE +1 386 GPIFSGLDATLX DATA 0BEH
00BF +1 387 GPIFSGLDATLNOX DATA 0BFH
A51 MACRO ASSEMBLER EEPROMA 11/07/2006 14:52:11 PAGE 7
+1 388
00C0 +1 389 SCON1 DATA 0C0H
+1 390 ; SCON1
00C0 +1 391 RI1 BIT 0C0H+0H
00C1 +1 392 TI1 BIT 0C0H+1H
00C2 +1 393 RB81 BIT 0C0H+2H
00C3 +1 394 TB81 BIT 0C0H+3H
00C4 +1 395 REN1 BIT 0C0H+4H
00C5 +1 396 SM21 BIT 0C0H+5H
00C6 +1 397 SM11 BIT 0C0H+6H
00C7 +1 398 SM01 BIT 0C0H+7H
00C1 +1 399 SBUF1 DATA 0C1H
00C8 +1 400 T2CON DATA 0C8H
+1 401 ; T2CON
00C8 +1 402 CP_RL2 BIT 0C8H+0H
00C9 +1 403 C_T2 BIT 0C8H+1H
00CA +1 404 TR2 BIT 0C8H+2H
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