📄 gpif.lst
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231 1
232 1 GPIFWFSELECT = (1 << 4); // PIO read is waveform 1
233 1
234 1 // put out address of interest
235 1 OUTATAPI = addr | (~ATAPI_ADDR_MASK & ATAPI_IDLE_VALUE);
236 1
237 1 // trigger the GPIF
238 1 retval = XGPIFSGLDATLX; // Single bus transaction on the GPIF
239 1
C51 COMPILER V7.50 GPIF 11/07/2006 14:52:08 PAGE 5
240 1 while (!gpifIdle()); // wait till GPIF is done before getting real data
241 1
242 1 retval = (XGPIFSGLDATLNOX << 8) + XGPIFSGLDATH; // get data from last GPIF transaction
243 1 OUTATAPI = ATAPI_IDLE_VALUE; // Clear the address/chip selects
244 1
245 1 return(retval);
246 1 }
247
248
249 // Read a string from the given disk register or buffer
250 void readPIO16(char addr, WORD count)
251 {
252 1 // check for GPIF ready
253 1 while (!gpifIdle());
254 1
255 1 GPIFWFSELECT = (1); // PIO read is waveform 1
256 1
257 1 // Write the address/chip selects
258 1 OUTATAPI = addr | (~ATAPI_ADDR_MASK & ATAPI_IDLE_VALUE);
259 1
260 1 // set up for GPIF transfer - wordwide, so count/2
261 1 EP8GPIFTCH = MSB(count >> 1);
262 1 EP8GPIFTCL = LSB(count >> 1);
263 1
264 1 // trigger GPIF. No longer wait 'til done
265 1 GPIFTRIG = 0x07; // GPIFTRIG[2] = RD/WR BIT (1 = READ)
266 1 // GPIFTRIG[1..0] = EP#, 00=ep2, 01=ep4, 10 = ep6, 11=ep8
267 1
268 1 }
269
270 // read count WORDs using UDMA
271 void readUDMA(DWORD count)
272 {
273 1 // check for GPIF ready
274 1 while (!gpifIdle());
275 1
276 1 GPIFWFSELECT = (3); // UDMA read is waveform 3
277 1
278 1 // Write the address/chip selects -- Note that this is not the same register as the ATAPI_DATA_REG
279 1 OUTATAPI = CS(3) | DA(0) | (~ATAPI_ADDR_MASK & ATAPI_IDLE_VALUE);
280 1
281 1 // set up for GPIF transfer - wordwide
282 1 GPIFTCB3 = 0;
283 1 GPIFTCB2 = ((BYTE *) &count)[1];
284 1 GPIFTCB1 = ((BYTE *) &count)[2];
285 1 GPIFTCB0 = LSB(count);
286 1
287 1 FLOWSTATE = 0x82;
288 1
289 1 // trigger GPIF and wait till done
290 1 GPIFTRIG = 0x07; // GPIFTRIG[2] = RD/WR BIT (1 = READ)
291 1 // GPIFTRIG[1..0] = EP#, 00=ep2, 01=ep4, 10 = ep6, 11=ep8
292 1
293 1 // Wait for the drive interrupt.
294 1 while(!(IOA & 0x01));
295 1
296 1 if (!gpifIdle())
297 1 {
298 2 abortGPIF();
299 2 }
300 1
301 1 FLOWSTATE = 0x00;
C51 COMPILER V7.50 GPIF 11/07/2006 14:52:08 PAGE 6
302 1 }
303
304 // Wait for all of the bulk buffers to be full (or all of the data to be received)
305 // Switch to manual mode
306 // Write count WORDs using UDMA
307 // Return drive status
308 void writeUDMA(DWORD count)
309 {
310 1 BYTE drvstat=0;
311 1 WORD byteCount;
312 1 BYTE i;
313 1
314 1 // Special code for switching between auto/manual modes. Make sure that all of
315 1 // the buffers are full before switching.
316 1 for (i = 0, byteCount = 0; i < 4 && byteCount < dataTransferLen; i++, byteCount +=wPacketSize)
317 1 {
318 2 // wait for the sector to show up
319 2 while ((EP2CS & bmEPEMPTY))
320 2 ;
321 2
322 2 // commit the buffer(s) to the GPIF
323 2 EP2BCL = 0x00;
324 2 WRITEDELAY();
325 2 }
326 1
327 1 initUdmaWrite();
328 1
329 1 EP2FIFOCFG = bmAUTOOUT | bmWORDWIDE;
330 1
331 1 // check for GPIF ready
332 1 while (!gpifIdle());
333 1
334 1 GPIFWFSELECT = (2 << 2); // UDMA write is waveform 2
335 1
336 1 // Write the address/chip selects -- Note that this is not the same register as the ATAPI_DATA_REG
337 1 OUTATAPI = CS(3) | DA(0) | (~ATAPI_ADDR_MASK & ATAPI_IDLE_VALUE);
338 1
339 1 // set up for GPIF transfer - wordwide
340 1 GPIFTCB3 = 0;
341 1 GPIFTCB2 = ((BYTE *) &count)[1];
342 1 GPIFTCB1 = ((BYTE *) &count)[2];
343 1 GPIFTCB0 = LSB(count);
344 1
345 1 FLOWSTATE = 0x83;
346 1
347 1 // trigger GPIF and wait till done
348 1 EP2GPIFTRIG = 0;
349 1
350 1 // Wait for the drive interrupt.
351 1 while( !((drvstat = IOA) & 0x01))
352 1 ;
353 1
354 1 if (!gpifIdle())
355 1 {
356 2 abortGPIF();
357 2 }
358 1
359 1 FLOWSTATE = 0x00;
360 1
361 1 // cancel AUTO OUT mode
362 1 EP2FIFOCFG = bmWORDWIDE;
363 1 WRITEDELAY();
C51 COMPILER V7.50 GPIF 11/07/2006 14:52:08 PAGE 7
364 1 }
365
366 void abortGPIF()
367 {
368 1 FLOWSTATE = 0x00; // xro - take out of UDMA flowstate
369 1 GPIFABORT = 0xff;
370 1
371 1 // reset the transaction count state machine, in FX2 revs up to and
372 1 // including Rev D, there is a bug that prevents the GPIF state machine
373 1 // from properly reseting following an abort. The following code is a
374 1 // workaround for this problem. See the FX2 chip errata for details.
375 1 #ifdef GPIF_ABORT_BUG_PRESENT
mymemmovexx(&GPIF_WAVE_DATA, (BYTE xdata *) AbortWave, sizeof(WaveDataPio4));
GPIFWFSELECT = 0; // PIO write is waveform 0
EP2GPIFTCH = 0;
EP2GPIFTCL = 1;
GPIFSGLDATLX = 0;
mymemmovexx(&GPIF_WAVE_DATA, (BYTE xdata *) WaveDataPio4, sizeof(WaveDataPio4));
#endif
386 1 }
387
C51 COMPILER V7.50 GPIF 11/07/2006 14:52:08 PAGE 8
ASSEMBLY LISTING OF GENERATED OBJECT CODE
; FUNCTION hardwareReset (BEGIN)
; SOURCE LINE # 102
; SOURCE LINE # 103
; SOURCE LINE # 104
0000 53807F ANL IOA,#07FH
; SOURCE LINE # 105
0003 7F64 MOV R7,#064H
0005 7E00 MOV R6,#00H
0007 120000 E LCALL _EZUSB_Delay
; SOURCE LINE # 106
000A 438080 ORL IOA,#080H
; SOURCE LINE # 107
000D 22 RET
; FUNCTION hardwareReset (END)
; FUNCTION initUdmaRead (BEGIN)
; SOURCE LINE # 110
; SOURCE LINE # 111
; SOURCE LINE # 113
0000 90E6C7 MOV DPTR,#0E6C7H
0003 7436 MOV A,#036H
0005 F0 MOVX @DPTR,A
; SOURCE LINE # 114
0006 A3 INC DPTR
0007 E4 CLR A
0008 F0 MOVX @DPTR,A
; SOURCE LINE # 115
0009 A3 INC DPTR
000A 7402 MOV A,#02H
000C F0 MOVX @DPTR,A
; SOURCE LINE # 116
000D 90E6CB MOV DPTR,#0E6CBH
0010 74D0 MOV A,#0D0H
0012 F0 MOVX @DPTR,A
; SOURCE LINE # 117
0013 A3 INC DPTR
0014 7403 MOV A,#03H
0016 F0 MOVX @DPTR,A
; SOURCE LINE # 118
0017 90E60C MOV DPTR,#0E60CH
001A 7401 MOV A,#01H
001C F0 MOVX @DPTR,A
; SOURCE LINE # 120
001D 90E61B MOV DPTR,#0E61BH
0020 740D MOV A,#0DH
0022 F0 MOVX @DPTR,A
; SOURCE LINE # 121
0023 90E601 MOV DPTR,#0E601H
0026 74C6 MOV A,#0C6H
0028 F0 MOVX @DPTR,A
; SOURCE LINE # 122
0029 22 RET
; FUNCTION initUdmaRead (END)
; FUNCTION initUdmaWrite (BEGIN)
; SOURCE LINE # 124
; SOURCE LINE # 125
; SOURCE LINE # 126
0000 90E6C7 MOV DPTR,#0E6C7H
C51 COMPILER V7.50 GPIF 11/07/2006 14:52:08 PAGE 9
0003 7470 MOV A,#070H
0005 F0 MOVX @DPTR,A
; SOURCE LINE # 127
0006 A3 INC DPTR
0007 E4 CLR A
0008 F0 MOVX @DPTR,A
; SOURCE LINE # 128
0009 A3 INC DPTR
000A 7408 MOV A,#08H
000C F0 MOVX @DPTR,A
; SOURCE LINE # 129
000D 90E6CB MOV DPTR,#0E6CBH
0010 7411 MOV A,#011H
0012 F0 MOVX @DPTR,A
; SOURCE LINE # 130
0013 A3 INC DPTR
0014 7403 MOV A,#03H
0016 F0 MOVX @DPTR,A
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