dsk_app.c

一个具有很强通用性的在C6713上运行的源程序。

#define CHIP_6713
//#include "main.h"
#include <stdio.h>
#include <csl.h>
#include <csl_edma.h>
#include <csl_irq.h>
#include <csl_mcbsp.h>
#include <csl_gpio.h>
#include <csl_pll.h>
#include <csl_emif.h>
//#include <csl_emifhal.h>


//算法头文件
/*
#ifdef _WIN32
#include <windows.h>
#endif
//#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include "fastrts67x.h"
//#include <math.h>
#include <log.h>
#include "dm_process.h"

#ifdef _WIN32
#include <memory.h>
#endif

#include "prob.h"
#include "IMCRA.h"
#include "dualmic.h"
#include "fft_support.h"
#include "DSPF_sp_cfftr2_dit.h"
#include "DSPF_sp_icfftr2_dif.h"*/



/* Function prototypes */
void initIrq(void);
void initMcbsp(void);
void initEdma(void);

void copyData(Int32 *inbuf, Int32 *outbuf, Int32 length);
/*
void copyData_1(Int32 *inbuf, Int16 *outbuf, Int32 length);
void copyData_2(Int16 *inbuf, Int32 *outbuf, Int32 length);
*/

void processBuffer(Uint32 pingPong);
void mypll_init(void);
void setupInterrupts(void);
void init_emif( void );
void Delay(unsigned int nDelay);
//void set_data(void);
extern far void vectors();
void config_serial_1(void);
void do_switch(void);
/* Constants for the buffered ping-pong transfer */


#define PING 0
#define PONG 1
#define EMIF_GCTL       0x01800000
#define EMIF_CE1        0x01800004
#define EMIF_CE0        0x01800008
#define EMIF_CE2        0x01800010
#define EMIF_CE3        0x01800014
#define EMIF_SDRAMCTL   0x01800018
#define EMIF_SDRAMTIM   0x0180001C
#define EMIF_SDRAMEXT   0x01800020
#define EMIF_CCFG       0x01840000;
#define LBDS (*(unsigned int *)0x90100000)

//算法buffsize
//#define BUFFSIZE 2048
#define DM_FRAMELENGTH 2048
#define BUFFSIZE DM_FRAMELENGTH
/*
 * Data buffer declarations - the program uses four logical buffers of size
 * BUFFSIZE, one ping and one pong buffer on both receive and transmit sides.
 */

Int32 gBufferXmtPing[BUFFSIZE];  // Transmit PING buffer
Int32 gBufferXmtPong[BUFFSIZE];  // Transmit PONG buffer
Int32 gBufferRcvPing[BUFFSIZE];  // Receive PING buffer
Int32 gBufferRcvPong[BUFFSIZE];  // Receive PONG buffer
//Int32 gBufferData[BUFFSIZE];
/*
short gBufferXmtPing[BUFFSIZE];  // Transmit PING buffer
short gBufferXmtPong[BUFFSIZE];  // Transmit PONG buffer
short gBufferRcvPing[BUFFSIZE];  // Receive PING buffer
short gBufferRcvPong[BUFFSIZE];  // Receive PONG buffer
short gBufferData[BUFFSIZE];
*/

//short OutputBuffer[BUFFSIZE];  //算法输出BUFFER
//short InputBuffer[BUFFSIZE];    //算法输入BUFFER
//int OutputBuffer[BUFFSIZE];  //算法输出BUFFER
//int InputBuffer[BUFFSIZE];    //算法输入BUFFER
// 中转buffer
//short temp[BUFFSIZE/2];

int   memory_return =0;
int   copy_i;






EDMA_Handle hEdmaXmt;            // EDMA channel handles
EDMA_Handle hEdmaReloadXmtPing;
EDMA_Handle hEdmaReloadXmtPong;
EDMA_Handle hEdmaRcv;
EDMA_Handle hEdmaReloadRcvPing;
EDMA_Handle hEdmaReloadRcvPong;

MCBSP_Handle hMcbsp0;                 // McBSP0 (codec data) handle
MCBSP_Handle hMcbsp1; 
GPIO_Handle hGpio;
Int16 gXmtChan;                       // TCC codes (see initEDMA()) 
Int16 gRcvChan;
int wdg_flag;
int wdg_value;
Uint32 gpio_value_kb;
Uint32 gpio_value_gm;
Uint32 gpio_value_gl;
int last_value;
int led_paoma_flag;
int ii;
int gpio_flag;
int volme_ml;
unsigned short int uWork[4]={ 1,2,4,8 };
int led_value=8;
float volme_gain_coefficient[9]={1,1.1,1.21,1.331,1.4641,1.61051,1.77156,1.94872,2.14359};
/*
 *  EDMA Config data structure 
 */
 
/* Transmit side EDMA configuration */
EDMA_Config gEdmaConfigXmt = {  
    EDMA_FMKS(OPT, PRI, HIGH)          |  // Priority
    EDMA_FMKS(OPT, ESIZE, 32BIT)       |  // Element size
    EDMA_FMKS(OPT, 2DS, NO)            |  // 2 dimensional source?
    EDMA_FMKS(OPT, SUM, INC)           |  // Src update mode
    EDMA_FMKS(OPT, 2DD, NO)            |  // 2 dimensional dest
    EDMA_FMKS(OPT, DUM, NONE)          |  // Dest update mode
    EDMA_FMKS(OPT, TCINT, YES)         |  // Cause EDMA interrupt?
    EDMA_FMKS(OPT, TCC, OF(0))         |  // Transfer complete code
    EDMA_FMKS(OPT, LINK, YES)          |  // Enable link parameters?
    EDMA_FMKS(OPT, FS, NO),               // Use frame sync?

    (Uint32)&gBufferXmtPing,              // Src address

    EDMA_FMK (CNT, FRMCNT, NULL)       |  // Frame count
    EDMA_FMK (CNT, ELECNT, BUFFSIZE),     // Element count
    
    EDMA_FMKS(DST, DST, OF(0)),           // Dest address

    EDMA_FMKS(IDX, FRMIDX, DEFAULT)    |  // Frame index value
    EDMA_FMKS(IDX, ELEIDX, DEFAULT),      // Element index value

    EDMA_FMK (RLD, ELERLD, NULL)       |  // Reload element
    EDMA_FMK (RLD, LINK, NULL)            // Reload link
};

/* Receive side EDMA configuration */
EDMA_Config gEdmaConfigRcv = {  
    EDMA_FMKS(OPT, PRI, HIGH)          |  // Priority
    EDMA_FMKS(OPT, ESIZE, 32BIT)       |  // Element size
    EDMA_FMKS(OPT, 2DS, NO)            |  // 2 dimensional source?
    EDMA_FMKS(OPT, SUM, NONE)          |  // Src update mode
    EDMA_FMKS(OPT, 2DD, NO)            |  // 2 dimensional dest
    EDMA_FMKS(OPT, DUM, INC)           |  // Dest update mode
    EDMA_FMKS(OPT, TCINT, YES)         |  // Cause EDMA interrupt?
    EDMA_FMKS(OPT, TCC, OF(0))         |  // Transfer complete code
    EDMA_FMKS(OPT, LINK, YES)          |  // Enable link parameters?
    EDMA_FMKS(OPT, FS, NO),               // Use frame sync?
    
    EDMA_FMKS(SRC, SRC, OF(0)),           // Src address
 
    EDMA_FMK (CNT, FRMCNT, NULL)       |  // Frame count 
    EDMA_FMK (CNT, ELECNT, BUFFSIZE),     // Element count
    
    (Uint32)&gBufferRcvPing,              // Dest address
          
    EDMA_FMKS(IDX, FRMIDX, DEFAULT)    |  // Frame index value
    EDMA_FMKS(IDX, ELEIDX, DEFAULT),      // Element index value

    EDMA_FMK (RLD, ELERLD, NULL)       |  // Reload element
    EDMA_FMK (RLD, LINK, NULL)            // Reload link
};

/* McBSP codec data channel configuration */
static MCBSP_Config mcbspCfg0 = {
        MCBSP_FMKS(SPCR, FREE, YES)              |
        MCBSP_FMKS(SPCR, SOFT, YES)              |
        MCBSP_FMKS(SPCR, FRST, YES)             |
        MCBSP_FMKS(SPCR, GRST, YES)             |
        MCBSP_FMKS(SPCR, XINTM, XRDY)           |
        MCBSP_FMKS(SPCR, XSYNCERR, NO)          |
        MCBSP_FMKS(SPCR, XRST, YES)             |
        MCBSP_FMKS(SPCR, DLB, OFF)              |
        MCBSP_FMKS(SPCR, RJUST, RZF)            |
        MCBSP_FMKS(SPCR, CLKSTP, DISABLE)       |
        MCBSP_FMKS(SPCR, DXENA, OFF)            |
        MCBSP_FMKS(SPCR, RINTM, RRDY)           |
        MCBSP_FMKS(SPCR, RSYNCERR, NO)          |
        MCBSP_FMKS(SPCR, RRST, YES),

        MCBSP_FMKS(RCR, RPHASE, DUAL)         |
        MCBSP_FMKS(RCR, RFRLEN2, DEFAULT)       |
        MCBSP_FMKS(RCR, RWDLEN2, 32BIT)       |
        MCBSP_FMKS(RCR, RCOMPAND, MSB)          |
        MCBSP_FMKS(RCR, RFIG, YES)               |
        MCBSP_FMKS(RCR, RDATDLY, 0BIT)          |
        MCBSP_FMKS(RCR, RFRLEN1, OF(0))         |
        MCBSP_FMKS(RCR, RWDLEN1, 32BIT)         |
        MCBSP_FMKS(RCR, RWDREVRS, DISABLE),

        MCBSP_FMKS(XCR, XPHASE, DUAL)         |
        MCBSP_FMKS(XCR, XFRLEN2, DEFAULT)       |
        MCBSP_FMKS(XCR, XWDLEN2, 32BIT)       |
        MCBSP_FMKS(XCR, XCOMPAND, MSB)          |
        MCBSP_FMKS(XCR, XFIG, YES)               |
        MCBSP_FMKS(XCR, XDATDLY, 0BIT)          |
        MCBSP_FMKS(XCR, XFRLEN1, OF(0))         |
        MCBSP_FMKS(XCR, XWDLEN1, 32BIT)         |
        MCBSP_FMKS(XCR, XWDREVRS, DISABLE),
        
        MCBSP_FMKS(SRGR, GSYNC, FREE)        |
        MCBSP_FMKS(SRGR, CLKSP, RISING)        |
        MCBSP_FMKS(SRGR, CLKSM, CLKS)        |
        MCBSP_FMKS(SRGR, FSGM, FSG)         |
        MCBSP_FMKS(SRGR, FPER,  OF(63))         |
        MCBSP_FMKS(SRGR, FWID, OF(31))         |
        MCBSP_FMKS(SRGR, CLKGDV, OF(3)),

        MCBSP_MCR_DEFAULT,
        MCBSP_RCER_DEFAULT,
        MCBSP_XCER_DEFAULT,

        MCBSP_FMKS(PCR, XIOEN, SP)              |
        MCBSP_FMKS(PCR, RIOEN, SP)              |
        MCBSP_FMKS(PCR, FSXM, INTERNAL)         |
        MCBSP_FMKS(PCR, FSRM, INTERNAL)         |
        MCBSP_FMKS(PCR, CLKXM, OUTPUT)           |
        MCBSP_FMKS(PCR, CLKRM, OUTPUT)           |
        MCBSP_FMKS(PCR, CLKSSTAT, DEFAULT)      |
        MCBSP_FMKS(PCR, DXSTAT, DEFAULT)        |
        MCBSP_FMKS(PCR, FSXP, ACTIVEHIGH)       |
        MCBSP_FMKS(PCR, FSRP, ACTIVEHIGH)       |
        MCBSP_FMKS(PCR, CLKXP, RISING )         |
        MCBSP_FMKS(PCR, CLKRP, FALLING )
};

/* McBSP codec data channel configuration */
static MCBSP_Config mcbspCfg1 = {
        MCBSP_FMKS(SPCR, FREE, YES)              |
        MCBSP_FMKS(SPCR, SOFT, YES)              |
        MCBSP_FMKS(SPCR, FRST, YES)             |
        MCBSP_FMKS(SPCR, GRST, YES)             |
        MCBSP_FMKS(SPCR, XINTM, XRDY)           |
        MCBSP_FMKS(SPCR, XSYNCERR, NO)          |
        MCBSP_FMKS(SPCR, XRST, YES)             |
        MCBSP_FMKS(SPCR, DLB, OFF)              |
        MCBSP_FMKS(SPCR, RJUST, RZF)            |
        MCBSP_FMKS(SPCR, CLKSTP, DISABLE)       |
        MCBSP_FMKS(SPCR, DXENA, OFF)            |
        MCBSP_FMKS(SPCR, RINTM, RRDY)           |
        MCBSP_FMKS(SPCR, RSYNCERR, NO)          |
        MCBSP_FMKS(SPCR, RRST, YES),

        MCBSP_FMKS(RCR, RPHASE, DUAL)         |
        MCBSP_FMKS(RCR, RFRLEN2, DEFAULT)       |
        MCBSP_FMKS(RCR, RWDLEN2, 32BIT)       |
        MCBSP_FMKS(RCR, RCOMPAND, MSB)          |
        MCBSP_FMKS(RCR, RFIG, YES)               |
        MCBSP_FMKS(RCR, RDATDLY, 0BIT)          |
        MCBSP_FMKS(RCR, RFRLEN1, OF(0))         |
        MCBSP_FMKS(RCR, RWDLEN1, 32BIT)         |
        MCBSP_FMKS(RCR, RWDREVRS, DISABLE),

        MCBSP_FMKS(XCR, XPHASE, DUAL)         |
        MCBSP_FMKS(XCR, XFRLEN2, DEFAULT)       |
        MCBSP_FMKS(XCR, XWDLEN2, 32BIT)       |
        MCBSP_FMKS(XCR, XCOMPAND, MSB)          |
        MCBSP_FMKS(XCR, XFIG, YES)               |
        MCBSP_FMKS(XCR, XDATDLY, 0BIT)          |
        MCBSP_FMKS(XCR, XFRLEN1, OF(0))         |
        MCBSP_FMKS(XCR, XWDLEN1, 32BIT)         |
        MCBSP_FMKS(XCR, XWDREVRS, DISABLE),
        
        MCBSP_FMKS(SRGR, GSYNC, FREE)        |
        MCBSP_FMKS(SRGR, CLKSP, RISING)        |
        MCBSP_FMKS(SRGR, CLKSM, CLKS)        |
        MCBSP_FMKS(SRGR, FSGM, FSG)         |
        MCBSP_FMKS(SRGR, FPER,  OF(63))         |
        MCBSP_FMKS(SRGR, FWID, OF(31))         |
        MCBSP_FMKS(SRGR, CLKGDV, OF(3)),

        MCBSP_MCR_DEFAULT,
        MCBSP_RCER_DEFAULT,
        MCBSP_XCER_DEFAULT,

        MCBSP_FMKS(PCR, XIOEN, SP)              |
        MCBSP_FMKS(PCR, RIOEN, SP)              |
        MCBSP_FMKS(PCR, FSXM, INTERNAL)         |
        MCBSP_FMKS(PCR, FSRM, INTERNAL)         |
        MCBSP_FMKS(PCR, CLKXM, OUTPUT)           |
        MCBSP_FMKS(PCR, CLKRM, OUTPUT)           |
        MCBSP_FMKS(PCR, CLKSSTAT, DEFAULT)      |
        MCBSP_FMKS(PCR, DXSTAT, DEFAULT)        |
        MCBSP_FMKS(PCR, FSXP, ACTIVEHIGH)       |
        MCBSP_FMKS(PCR, FSRP, ACTIVELOW)       |
        MCBSP_FMKS(PCR, CLKXP, FALLING )         |
        MCBSP_FMKS(PCR, CLKRP, RISING )
};

/* --------------------------- main() function -------------------------- */
/*
 *  main() - The main user task.  Performs application initialization and
 *           starts the data transfer.
 */
void main()
{
	
  	unsigned short *pdata;  	
    /* Initialize Board Support Library */
    init_emif();
    
    
    /* SEED的6713板MCBSP和MCASP复用，用模板控制寄存器DECCLT控制，DECCLT.6为高，则选择MCBSP */   
    pdata = (unsigned short *)(0xb0000000);
	*pdata = 0x40;

    /* Initialize the chip support library, must when using CSL */    
    CSL_init();
/***************************************************************************/
	hGpio = GPIO_open(GPIO_DEV0,GPIO_OPEN_RESET);
	
	GPIO_configArgs(hGpio,
	0x00000030, /* gpgc */
	0x0000be00, /* gpen */
	0x0000b000, /* gdir */
	0x00000000, /* gpval */
	0x00000e00, /* gphm */
	0x00000e00, /* gplm */
	0x00000000  /* gppol */
	);
    GPIO_pinWrite(hGpio,GPIO_PIN15,1);
    Delay(1000);
    GPIO_pinWrite(hGpio,GPIO_PIN15,0);
    GPIO_pinWrite(hGpio,GPIO_PIN13,1);
    gpio_value_kb  =GPIO_pinRead(hGpio,GPIO_PIN9);
  	gpio_value_gm =GPIO_pinRead(hGpio,GPIO_PIN10);
 	gpio_value_gl =GPIO_pinRead(hGpio,GPIO_PIN11);
/**************************************************************************/    
    mypll_init();

    setupInterrupts();
    /* Clear buffers */
    memset((void *)gBufferXmtPing, 0, BUFFSIZE * 4 * 2);
    
    initMcbsp();               // Initialize McBSP0 for audio transfers

    IRQ_globalDisable();       // Disable global interrupts during setup

    initEdma();                // Initialize the EDMA controller

    initIrq();                 // Initialize interrupts
    
    //    memory_return = dm_init(0.1, 0.5);    // //初始化算法参数
	
    
    
    IRQ_globalEnable();        // Re-enable global interrupts
/**********************MAIN CIRCRE*****************************************/
wdg_flag=0;
wdg_value=0;
gpio_flag=0;
ii=0;
volme_ml=0;
while(1)
{
   if (wdg_flag==1)
		{ 	GPIO_pinWrite(hGpio,GPIO_PIN12,wdg_value);
			wdg_flag=0;	
				if (wdg_value==0)
					wdg_value=1;
				else
					wdg_value=0;
		}
   if(led_paoma_flag==1)
  		{
  			last_value=LBDS;
			LBDS=(uWork[ii]&0x7)|(last_value&0x8);
			ii++; 
			ii%=3;
        	led_paoma_flag=0;
  		}	 
   if (gpio_flag==1)
   		{
			do_switch();
    		gpio_flag=0;
   	    	LBDS=led_value;
        	led_value=~led_value;
   		} 

}
/*************************************************************************/
}
/* ------------------------Helper Functions ----------------------------- */ 

/*
 *  initMcbsp() - Initialize the McBSP for codec data transfers using the
 *                configuration define at the top of this file.
 */
void initMcbsp()
{
    /* Open the codec data McBSP */
    hMcbsp0 = MCBSP_open(MCBSP_DEV0, MCBSP_OPEN_RESET);

    /* Configure the codec to match the ad da data format */
    MCBSP_config(hMcbsp0, &mcbspCfg0);

    /* Start the McBSP running */
    MCBSP_start(hMcbsp0, MCBSP_XMIT_START|