clknkto2m_rtl.vhd

一种方便的全数字时钟频率转换电路设计

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

ENTITY clknkto2m IS
   port (
        --Input
        rst_n_i    : in std_logic;
        clk_lc65_i : in std_logic;
        clk_nk_i   : in std_logic;
        slotnum_i  : in std_logic_vector(4 downto 0);
        
        --Output
        clk_2m_o   : out std_logic
    );
END ENTITY clknkto2m;

--
ARCHITECTURE rtl OF clknkto2m IS
signal clknksft : std_logic_vector(2 downto 0);
  signal clknkcnt : std_logic_vector(4 downto 0); -- counter to divide 64kN 
  signal clk64k   : std_logic; --divided from 64kN
  
  signal clk65mto2mcnt : std_logic_vector(4 downto 0); -- 32-div or 33-div 65m to 2m
  signal clk2mto64kcnt : std_logic_vector(4 downto 0); -- divide 2m to 64k
  
  signal stopcntpulse : std_logic; --stop clk65mto2mcnt, to gen 33-div 65m to 2m
  signal clk64ksample : std_logic; --sample 64k clk to get rising edge 
begin
  --64kN -> 64k
process(rst_n_i,clk_lc65_i)--clknkcnt
begin
	if clk_lc65_i'event and clk_lc65_i='1' then
	    clknksft <= clknksft(1 downto 0) & clk_nk_i;
	    if (clknksft(2 downto 1)="01") then
  			if clknkcnt=slotnum_i then
  				clknkcnt <= (others=>'0');
  			else
  				clknkcnt <= clknkcnt + 1;
  			end if;
  	    end if;
	end if;
	if rst_n_i='0' then
	    clknksft <= (others=>'0');
		clknkcnt <= (others=>'0');
	end if;
end process;

process(clk_lc65_i)
begin
	if clk_lc65_i'event and clk_lc65_i='1' then
		if slotnum_i(4)='1' then
			clk64k <= clknkcnt(4);
		elsif slotnum_i(3)='1' then
			clk64k <= clknkcnt(3);
		elsif slotnum_i(2)='1' then
			clk64k <= clknkcnt(2);
		elsif slotnum_i(1)='1' then
			clk64k <= clknkcnt(1);
		elsif slotnum_i(0)='1' then
			clk64k <= clknkcnt(0);
		else
			clk64k <= clknksft(1);
		end if;
	end if;
end process;

  -- 65m->2m, 2m->64k
clk_2m_o <= clk65mto2mcnt(4);
process(rst_n_i,clk_lc65_i) --clk65mto2mcnt
begin
	if clk_lc65_i'event and clk_lc65_i='1' then
		if stopcntpulse='1' then
			clk65mto2mcnt <= clk65mto2mcnt;
		else
			clk65mto2mcnt <= clk65mto2mcnt + 1;
		end if;
		
		if clk65mto2mcnt=31 then
			clk2mto64kcnt <= clk2mto64kcnt + 1;
		end if;
	end if;
	if rst_n_i='0' then
		clk65mto2mcnt <= (others=>'0');
		clk2mto64kcnt <= (others=>'0');
	end if;
end process;

  -- compare phase of two 64k clocks
process(rst_n_i,clk_lc65_i) -- compare phase: sample 64kNto64k and 2mTo64k, then gen stopcntpulse
begin
	if clk_lc65_i'event and clk_lc65_i='1' then
		clk64ksample <= clk64k;
		if stopcntpulse='1' then
			stopcntpulse <= '0';
		else
			if clk64ksample='0' and clk64k='1' and clk2mto64kcnt(4)='1' then
				stopcntpulse <= '1'; -- this pulse is only ONE 65m cycle wide
			end if;
		end if;
	end if;
	if rst_n_i='0' then
		clk64ksample <= '0';
		stopcntpulse <= '0';
	end if;
end process;
END ARCHITECTURE rtl;