timing_struct.vhd

一种方便的全数字时钟频率转换电路设计

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

ENTITY Timing IS
   
   port (
     --Input
     rst_n_i    : in std_logic;
     clk_lc65_i : in std_logic;
     clk_lc2m_i : in std_logic;
     e1dclk_i   : in std_logic;
     dterclk_i  : in std_logic;
     dtetclk_i  : in std_logic;
     v35lp_i    : in std_logic_vector(1 downto 0);
     chan16en_i : in std_logic;
     frmmode_i  : in std_logic;
     v35_mod_i  : in std_logic_vector(2 downto 0);
     ctrlhead_i : in std_logic_vector(4 downto 0);
     ctrltail_i : in std_logic_vector(4 downto 0);
     
     --Output
     e1aclk_o   : out std_logic;
     v35rclk_o  : out std_logic;
     v35tclk_o  : out std_logic;
     dcerclk_o  : out std_logic;
     dcetclk_o  : out std_logic;
     tp7         : OUT    std_logic;
     tp8         : OUT    std_logic;
     tp9         : OUT    std_logic
 );

-- Declarations

END Timing ;

--
ARCHITECTURE struct OF Timing IS
       -----------------------------
   

  component clknkto2m
      port (
          --Input
          rst_n_i    : in std_logic;
          clk_lc65_i : in std_logic;
          clk_nk_i   : in std_logic;
          slotnum_i  : in std_logic_vector(4 downto 0);
          
          --Output
          clk_2m_o   : out std_logic
      );
  end component;
  
  component clk2mtonk
     port (
             --Input
             rst_n_i    : in std_logic;
             clk_lc65_i : in std_logic;
             clk_2m_i   : in std_logic;
             slotnum_i  : in std_logic_vector(4 downto 0);
             --div_n_i    : in std_logic_vector(9 downto 0);
             --div_m_i    : in std_logic_vector(4 downto 0);
             
             --Output
             clk_nk_o   : out std_logic
         );
  end component;
  
  signal rdq : std_logic_vector(14 downto 0);
  signal slotnum : std_logic_vector(4 downto 0);
  
  signal clkdteg2m : std_logic;
  signal clknkloca : std_logic;
  signal clknkline : std_logic;
  
begin
  
  
  e1aclk_o<= e1dclk_i when v35_mod_i="001" else
             clkdteg2m when v35_mod_i="010" else
             clk_lc2m_i;
             
  dcerclk_o <= clknkloca  when v35_mod_i/="001" else
               clknkline;
  dcetclk_o <= clknkloca  when v35_mod_i/="001" and v35lp_i(0)='1' else 
               clknkline;
  
  v35rclk_o <= clknkline  when v35_mod_i="001" else 
               dterclk_i  when v35_mod_i="010" else
               clknkline  when v35lp_i(1)='1' else
               clknkloca;
  
               
  v35tclk_o <= dtetclk_i  when v35_mod_i="010" else
               clknkline;
  

  process(rst_n_i,clk_lc65_i)
  begin
      if (rst_n_i='0') then
          slotnum <= (others=>'0');
      elsif rising_edge(clk_lc65_i) then
          if (frmmode_i='0') then
              slotnum <= (others=>'1');
          else
              if (chan16en_i='1' or (chan16en_i='0' and (ctrlhead_i>16 or ctrltail_i<16))) then
                  slotnum <= ctrltail_i - ctrlhead_i;
              else
                  slotnum <= ctrltail_i - ctrlhead_i - 1;
              end if;
          end if;
      end if;
  end process;
  
 
  
  clknkto2m_inst : clknkto2m port map (
      rst_n_i    => rst_n_i,
      clk_lc65_i => clk_lc65_i,
      clk_nk_i   => dterclk_i,
      slotnum_i  => slotnum,
      clk_2m_o   => clkdteg2m
  );
  
  clk2mtonk_loc_inst : clk2mtonk port map (
      rst_n_i    => rst_n_i,
      clk_lc65_i => clk_lc65_i,
      clk_2m_i   => clk_lc2m_i,
      slotnum_i  => slotnum,
      clk_nk_o   => clknkloca
  );
  
  clk2mtonk_lin_inst : clk2mtonk port map (
      rst_n_i    => rst_n_i,
      clk_lc65_i => clk_lc65_i,
      clk_2m_i   => e1dclk_i,
      slotnum_i  => slotnum,
      clk_nk_o   => clknkline
  );


END ARCHITECTURE struct;