clk2mtonk_rtl.vhd

一种方便的全数字时钟频率转换电路设计

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;


ENTITY clk2mtonk IS
  port (
          --Input
          rst_n_i    : in std_logic;
          clk_lc65_i : in std_logic;
          clk_2m_i   : in std_logic;
          slotnum_i  : in std_logic_vector(4 downto 0);
          --div_n_i    : in std_logic_vector(9 downto 0);
          --div_m_i    : in std_logic_vector(4 downto 0);
          
          --Output
          clk_nk_o   : out std_logic
      );
END ENTITY clk2mtonk;

--
ARCHITECTURE rtl OF clk2mtonk IS
   signal dvi64kcnt : std_logic_vector(4 downto 0);
    signal clk64k    : std_logic; -- divided from 2m
    
    signal clk64ksft : std_logic_vector(2 downto 0);
    signal div65mcnt : std_logic_vector(9 downto 0);
    signal div_mcnt  : std_logic_vector(4 downto 0);
    
    signal Div_N        :std_logic_vector(9 downto 0);
    signal Div_m        :std_logic_vector(4 downto 0); 
    
    signal clk_nk : std_logic; -- gen clk_nk_o after 65m sample
begin
    -- div 2m to 64k, and get 64k rising edge (i.e. define start of every 64k cycle)
    clk64k <= dvi64kcnt(4);
	process(rst_n_i,clk_2m_i)--gen clk64k -- use 65m
	begin
		if clk_2m_i'event and clk_2m_i='1' then
			dvi64kcnt <= dvi64kcnt + 1;
		end if;
		if rst_n_i='0' then
			dvi64kcnt <= (others=>'0');
		end if;
	end process;
	
    --during every 64k cycle, gen N*64k aided by 65m
	process(rst_n_i,clk_lc65_i) --div_mcnt: a div_m_i counter, to amend 65m counter
	begin
		if clk_lc65_i'event and clk_lc65_i='1' then
		    clk64ksft <= clk64ksft(1 downto 0) & clk64k;
			if div65mcnt=div_n-1 then
				if div_mcnt=div_m-1 then
					div_mcnt <= (others=>'0');
				else
					div_mcnt <= div_mcnt + 1; 
				end if;
			end if;
			if clk64ksft(2 downto 1)="01" then
				div_mcnt <= (others=>'0');
			end if;
		end if;
		if rst_n_i='0' then
		    clk64ksft <= (others=>'0');
			div_mcnt  <= (others=>'0');
		end if;
	end process;
	
	process(rst_n_i,clk_lc65_i)--div65mcnt: a div_n_i counter, to divide 65m
	begin
		if clk_lc65_i'event and clk_lc65_i='1' then
			if div65mcnt=div_n-1 then
				if div_mcnt=div_m-1 then
					div65mcnt <= (others=>'1');-- this time div65mcnt become a (div_n_i + 1) conter
				else
					div65mcnt <= (others=>'0');
				end if;
			else
				div65mcnt <= div65mcnt + 1 ;
			end if;
			if clk64ksft(2 downto 1)="01" then
				div65mcnt <= (others=>'0');
			end if;
		end if;
		if rst_n_i='0' then
			div65mcnt <= (others=>'0');
		end if;
	end process;
	
	-- 2 * div_n_i * (N * 64k) = 65m
	clk_nk_o <= clk_nk;
	process(rst_n_i,clk_lc65_i) -- output clk64k*N
	begin
		if clk_lc65_i'event and clk_lc65_i='1' then
			if div65mcnt=div_n-1 then
				clk_nk <= not clk_nk;
			end if;
			if clk64ksft(2 downto 1)="01" then
				clk_nk <= '1';
			end if;
		end if;
		if rst_n_i='0' then  -- if no this rst_n_i, 'U' will be gen when sim
			clk_nk <= '1'; 
		end if;
	end process;
	
	----------------------------------------------------------------------
  --set Div_N, Div_m according to E1SlotSum
	  process(clk_lc65_i) -- Div_N, Div_m
	  begin
		  if clk_lc65_i'event and clk_lc65_i='1' then
			  case slotnum_i is
				  
				  when B"0_0000"=> Div_N<=B"10"&X"00"; Div_m<=B"0_0000";-- 512, [1/.125]>N 
				  when B"0_0001"=> Div_N<=B"01"&X"00"; Div_m<=B"0_0000";-- 256,16>N
				  when B"0_0010"=> Div_N<=B"00"&X"AA"; Div_m<=B"0_0010";-- 170, [1/.71]+1=2
				  when B"0_0011"=> Div_N<=B"00"&X"80"; Div_m<=B"0_0000";-- 128,32>N
				  
					  --sum of actually used e1 slot: 5,6,7,8
				  when B"0_0100"=> Div_N<=B"00"&X"66"; Div_m<=B"0_0011";-- 102, 3 
				  when B"0_0101"=> Div_N<=B"00"&X"55"; Div_m<=B"0_0011";-- 85, 3
				  when B"0_0110"=> Div_N<=B"00"&X"49"; Div_m<=B"0_0111";-- 73, 7=N
				  when B"0_0111"=> Div_N<=B"00"&X"40"; Div_m<=B"0_0000";-- 64, 64>N
  
					  --sum of actually used e1 slot: 9,10,11,12
				  when B"0_1000"=> Div_N<=B"00"&X"39"; Div_m<=B"0_0000";-- 57, 0 
				  when B"0_1001"=> Div_N<=B"00"&X"33"; Div_m<=B"0_0101";-- 51,5
				  when B"0_1010"=> Div_N<=B"00"&X"2E"; Div_m<=B"0_0010";-- 46,2
				  when B"0_1011"=> Div_N<=B"00"&X"2A"; Div_m<=B"0_0010";-- 42,2
  
					  --sum of actually used e1 slot: 13~16
				  when B"0_1100"=> Div_N<=B"00"&X"27"; Div_m<=B"0_0011";-- 39, 3 
				  when B"0_1101"=> Div_N<=B"00"&X"24"; Div_m<=B"0_0010";-- 36, 2
				  when B"0_1110"=> Div_N<=B"00"&X"22"; Div_m<=B"0_0111";-- 34, 7
				  when B"0_1111"=> Div_N<=B"00"&X"20"; Div_m<=B"0_0000";-- 32, 128>N
  
					  --sum of actually used e1 slot: 17~20
				  when B"1_0000"=> Div_N<=B"00"&X"1E"; Div_m<=B"0_1000";-- 30,8 
				  when B"1_0001"=> Div_N<=B"00"&X"1C"; Div_m<=B"0_0011";-- 28,3
				  when B"1_0010"=> Div_N<=B"00"&X"1B"; Div_m<=B"0_0000";-- 27,0
				  when B"1_0011"=> Div_N<=B"00"&X"19"; Div_m<=B"0_0010";-- 19,2
  
					  --sum of actually used e1 slot: 21~24
				  when B"1_0100"=> Div_N<=B"00"&X"18"; Div_m<=B"0_0011";-- 24, 3 
				  when B"1_0101"=> Div_N<=B"00"&X"17"; Div_m<=B"0_0100";-- 23, 4
				  when B"1_0110"=> Div_N<=B"00"&X"16"; Div_m<=B"0_0100";-- 22, 4
				  when B"1_0111"=> Div_N<=B"00"&X"15"; Div_m<=B"0_0011";-- 21, 3
  
					  --sum of actually used e1 slot: 25~28
				  when B"1_1000"=> Div_N<=B"00"&X"14"; Div_m<=B"0_0010";-- 20,2 
				  when B"1_1001"=> Div_N<=B"00"&X"13"; Div_m<=B"0_0010";-- 19,2
				  when B"1_1010"=> Div_N<=B"00"&X"13"; Div_m<=B"0_0000";-- 19,0
				  when B"1_1011"=> Div_N<=B"00"&X"12"; Div_m<=B"0_0100";-- 18,4
  
					  --sum of actually used e1 slot: 29~32
				  when B"1_1100"=> Div_N<=B"00"&X"11"; Div_m<=B"0_0010";-- 17, 2
				  when B"1_1101"=> Div_N<=B"00"&X"11"; Div_m<=B"0_1110";-- 17, 14
				  when B"1_1110"=> Div_N<=B"00"&X"10"; Div_m<=B"0_0010";-- 16, 2
				  when others=> --B"1_1111"=> 
								   Div_N<=B"00"&X"10"; Div_m<=B"0_0000";-- 16, 0
			  end case;
		  end if;
		end process;
END ARCHITECTURE rtl;