mu21k_hd.asm

dsp AD公司ADSP21的代码,里面有FFT FIR IIR EQULIZER G722_21F 等可以在项目中直接应用的代码.此代码的来源是ADI公司自己出版的书籍,此书在美国购得

            NOP;NOP;NOP;NOP;NOP;NOP;NOP;NOP;    /*Reserved interrupt    */
            NOP;NOP;NOP;NOP;NOP;NOP;NOP;NOP;    /*Reserved interrupt    */
            NOP;NOP;NOP;NOP;NOP;NOP;NOP;NOP;    /*Reserved interrupt    */

/* Interrupt vectors for user interrupts 0 - 7                      */
___lib_USR0I:       BIT CLR MODE1 0x1000;           /*Disable interrupts    */
            DM(I7,M7)=I13;              /*Save I13 (scratch reg)*/
            I13=DM(___lib_int_table+24*6+5);    /*addr of dispatch to jump to*/
            BIT SET MODE2 0x80000;          /*Freeze cache      */
            DM(I7,M7)=I15;              /*Save another scratch reg*/
            JUMP (M13, I13) (DB);           /*Jump to dispatcher    */
            I15=___lib_int_table+24*6;      /*Int slot next_mask    */
            I13=dm(___lib_int_table+24*6+2);    /*read addr of handler  */

___lib_USR1I:       BIT CLR MODE1 0x1000;           /*Disable interrupts    */
            DM(I7,M7)=I13;              /*Save I13 (scratch reg)*/
            I13=DM(___lib_int_table+25*6+5);    /*addr of dispatch to jump to*/
            BIT SET MODE2 0x80000;          /*Freeze cache      */
            DM(I7,M7)=I15;              /*Save another scratch reg*/
            JUMP (M13, I13) (DB);           /*Jump to dispatcher    */
            I15=___lib_int_table+25*6;      /*Int slot next_mask    */
            I13=dm(___lib_int_table+25*6+2);    /*read addr of handler  */

___lib_USR2I:       BIT CLR MODE1 0x1000;           /*Disable interrupts    */
            DM(I7,M7)=I13;              /*Save I13 (scratch reg)*/
            I13=DM(___lib_int_table+26*6+5);    /*addr of dispatch to jump to*/
            BIT SET MODE2 0x80000;          /*Freeze cache      */
            DM(I7,M7)=I15;              /*Save another scratch reg*/
            JUMP (M13, I13) (DB);           /*Jump to dispatcher    */
            I15=___lib_int_table+26*6;      /*Int slot next_mask    */
            I13=dm(___lib_int_table+26*6+2);    /*read addr of handler  */

___lib_USR3I:       BIT CLR MODE1 0x1000;           /*Disable interrupts    */
            DM(I7,M7)=I13;              /*Save I13 (scratch reg)*/
            I13=DM(___lib_int_table+27*6+5);    /*addr of dispatch to jump to*/
            BIT SET MODE2 0x80000;          /*Freeze cache      */
            DM(I7,M7)=I15;              /*Save another scratch reg*/
            JUMP (M13, I13) (DB);           /*Jump to dispatcher    */
            I15=___lib_int_table+27*6;      /*Int slot next_mask    */
            I13=dm(___lib_int_table+27*6+2);    /*read addr of handler  */

___lib_USR4I:       BIT CLR MODE1 0x1000;           /*Disable interrupts    */
            DM(I7,M7)=I13;              /*Save I13 (scratch reg)*/
            I13=DM(___lib_int_table+28*6+5);    /*addr of dispatch to jump to*/
            BIT SET MODE2 0x80000;          /*Freeze cache      */
            DM(I7,M7)=I15;              /*Save another scratch reg*/
            JUMP (M13, I13) (DB);           /*Jump to dispatcher    */
            I15=___lib_int_table+28*6;      /*Int slot next_mask    */
            I13=dm(___lib_int_table+28*6+2);    /*read addr of handler  */

___lib_USI15I:      BIT CLR MODE1 0x1000;           /*Disable interrupts    */
            DM(I7,M7)=I13;              /*Save I13 (scratch reg)*/
            I13=DM(___lib_int_table+29*6+5);    /*addr of dispatch to jump to*/
            BIT SET MODE2 0x80000;          /*Freeze cache      */
            DM(I7,M7)=I15;              /*Save another scratch reg*/
            JUMP (M13, I13) (DB);           /*Jump to dispatcher    */
            I15=___lib_int_table+29*6;      /*Int slot next_mask    */
            I13=dm(___lib_int_table+29*6+2);    /*read addr of handler  */

___lib_USR6I:       BIT CLR MODE1 0x1000;           /*Disable interrupts    */
            DM(I7,M7)=I13;              /*Save I13 (scratch reg)*/
            I13=DM(___lib_int_table+30*6+5);    /*addr of dispatch to jump to*/
            BIT SET MODE2 0x80000;          /*Freeze cache      */
            DM(I7,M7)=I15;              /*Save another scratch reg*/
            JUMP (M13, I13) (DB);           /*Jump to dispatcher    */
            I15=___lib_int_table+30*6;      /*Int slot next_mask    */
            I13=dm(___lib_int_table+30*6+2);    /*read addr of handler  */

___lib_USR7I:       BIT CLR MODE1 0x1000;           /*Disable interrupts    */
            DM(I7,M7)=I13;              /*Save I13 (scratch reg)*/
            I13=DM(___lib_int_table+31*6+5);    /*addr of dispatch to jump to*/
            BIT SET MODE2 0x80000;          /*Freeze cache      */
            DM(I7,M7)=I15;              /*Save another scratch reg*/
            JUMP (M13, I13) (DB);           /*Jump to dispatcher    */
            I15=___lib_int_table+31*6;      /*Int slot next_mask    */
            I13=dm(___lib_int_table+31*6+2);    /*read addr of handler  */

/* record interupt routine */

record:
        r3= (r4 + r3)/2;     { sum two inputs /2 to get one channel }
        r4 = r3 and r5;      { zero out bottom }

        r4=r4 or lshift r2 by -16;  { 2 16 bit -> 32 DM }
        r2 = r3;                    { save sample }

        bit tst ustat1 2;      { test if we have a record sample ready }
        if tf dm(i3,m1)=r4;    { store two samples }
        bit tgl ustat1 2;         { toggle the record ready flag }

/* determine if are doing simultaneous playback */

        bit tst astat FLG1; { test the flag 1 LED}
        if tf jump playback (DB);
        r4=dm(i0,0);       { get 2 samples }
        r3=lshift r4 by 16;     { get lower sample }

/* loop back mono during record only mode */

        rti (DB);
        dm(out_audio_r)=r2; { output AD1849 right value }
        dm(out_audio_l)=r2; { output AD1849 left value }

/* playback interupt routine, play r3 or r4 depending on ustat */

playback:
        bit tst ustat1 1;         { test if we have a sample ready }
        if not tf r3 = pass r4, modify(i0,m1);      { bump pointer }
        bit tgl ustat1 1;         { toggle the ready flag }
        rti (DB);
        dm(out_audio_r)=r3; { output AD1849 right value }
        dm(out_audio_l)=r3; { output AD1849 left value }

/* code to setup the hardware on the EZ-LAB board */

setup_ezlab:
        tperiod =0x004c4640;{ timer interrupt at 5 Hz }
        tcount  = tperiod;
        irptl   =0;     { clear any pending interrupts}

        ustat1 = 0;               { clear the user status registers }
        ustat2 = 0;

        bit clr mode1 IRPTEN;         { disable global int.}
        bit clr mode2 TIMEN;          { timer off! }

                { irq2,3 enable }
        bit set imask IRQ2I|IRQ3I;

                { irq2,3 edge sens, flag 1,2,3,outputs}
        bit set mode2 IRQ2E|IRQ3E|FLG1O|FLG2O|FLG3O;

                { turn flag LEDs off}
        bit clr astat FLG1|FLG2|FLG3;

        bit clr mode1 NESTM;          { no nested interupts }

/* set up interupt alternate registers */
        bit set mode1 SRD1L|SRD1H|SRRFL|SRRFH; { use all secondary registers}
        nop;

        i0=_play_fifo;           { output to D/A pointer (playback) }
        b0=i0;
        i1=_play_fifo;           { another circular pointer }
        b1=i1;
        i2=0;           { circular pointer for sendout }
        b2=i2;
        i3=_record_fifo;           { input from A/D pointer (record) }
        b3=i3;
        i4=_record_fifo;           { another circular pointer }
        b4=i4;
        i5=_record_fifo;           { another circular pointer }
        b5=i5;
        l0=FIFO_LENGTH;            { length for circular buffer }
        l1=FIFO_LENGTH;            { length for circular buffer }
        l2=FIFO_LENGTH;            { length for circular buffer }
        l3=FIFO_LENGTH;            { length for circular buffer }
        l4=FIFO_LENGTH;            { length for circular buffer }
        l5=FIFO_LENGTH;            { length for circular buffer }
        m1=1;                      { increment for sample buffer }
        r5=0xffff0000;             { and mask }

        bit clr mode1 SRD1L|SRD1H|SRRFL|SRRFH; { back to original registers}
        nop;

/* setup 1849, line input, low gain */
        r3 = 0x12110000;
        dm(control_0)=r3;

/* delay some */
        LCNTR=0xffff, DO (pc,10) UNTIL LCE;
        NOP;
        NOP;
        NOP;
        NOP;
        NOP;
        NOP;
        NOP;
        NOP;
        NOP;
        NOP;

/* sample rate default */
        r3 = CODEC_RATE_CODE;
        dm(control_1)=r3;

/* delay some */
        LCNTR=0xffff, DO (pc,10) UNTIL LCE;
        NOP;
        NOP;
        NOP;
        NOP;
        NOP;
        NOP;
        NOP;
        NOP;
        NOP;
        NOP;

/* zero output */
        r3 = 0;
        dm(out_audio_r)=r3; { output AD1849 right value }
        dm(out_audio_l)=r3; { output AD1849 left value }

        rts;

.ENDSEG;