ezset.asm

dsp AD公司ADSP21的代码,里面有FFT FIR IIR EQULIZER G722_21F 等可以在项目中直接应用的代码.此代码的来源是ADI公司自己出版的书籍,此书在美国购得

#include <def21060.h>
#include <asm_sprt.h>
#include "rtdsp.h"

/* code to setup the MAFE hardware on the SHARC EZ-LAB board */
/* also sets the alternate regs for IRQs during C code */

#define SPORT0_CHANNELS 16
#define SPORT0_BITS 16
#define DMA_CHANNELS 3

.segment /dm    mafeadrs;
.port   mafe_reset;             /* mafe reset port */
.endseg;

/* sample buffers for audio */
.SEGMENT/DM seg_dmda;

.global regs_1847;

/* default is line input, 32 KHz sample rate */

.var regs_1847[16] =
    0x8000,                 /* index 0 - left input control */
    0x8100,                 /* index 1 - right input control */
    0x8280,                 /* index 2 - left aux 1 input control */
    0x8380,                 /* index 3 - right aux 1 input control */
    0x8480,                 /* index 4 - left aux 2 input control */
    0x8580,                 /* index 5 - right aux 2 input control */
    0x8600,                 /* index 6 - left dac control */
    0x8700,                 /* index 7 - right dac control */
    0xc856,                 /* index 8 - data format */
    0xc909,                 /* index 9 - interface configuration */
    0x8a00,                 /* index 10 - pin control */
    0x8b00,                 /* index 11 - no register */
    0xccc0,                 /* index 12 - miscellaneous information */
    0x8d00,                 /* index 13 - digital mix control */
    0x8e00,                 /* intex 14 - no register */
    0x8f00;                 /* intex 15 - no register */

.VAR xtcb_beg0[7]=
                00000000,                       /* transmit chaining block */
                00000000,
                00000000,
                00000000,
                xmit_tcb0,
                DMA_CHANNELS,
                00000001;
.VAR xmit_tcb0= tx_buf0;

.VAR rtcb_beg0[7]=
                00000000,                       /* receive chaining block */
                00000000,
                00000000,
                00000000,
                rcvr_tcb0,
                DMA_CHANNELS,
                00000001;
.VAR rcvr_tcb0= rx_buf0;

.endseg;

.segment/pm seg_pmco;

.GLOBAL _ezset;

/* this gets called in the header file sharc_hd.asm */

_ezset:

    entry;

    bit clr mode1 IRPTEN;         { disable global int.}
    nop;

/* turn off nesting of iterrupts */
    bit clr mode1 NESTM;

    r0 = 0;
    dm(mafe_reset) = r0;            /* put mafe in reset */
    r0 = 3;
    dm(mafe_reset) = r0;            /* take mafe out of reset */

    tperiod = 5000000;              /* timer interrupt at 5 Hz */
    tcount = tperiod;

    irptl   =0;     { clear any pending interrupts}

    ustat1 = 0;               { clear the user status registers }
    ustat2 = 0;

/* flag 2 & 0 outputs irq1 edge sens */
    bit set mode2 FLG2O | FLG0O | IRQ1E;

    bit set astat FLG2 | FLG0;      /* turn flag LEDs off */

    bit set imask TMZHI | IRQ1I;    /* timer high priority & irq1 enabled */

    bit set mode2 TIMEN;            /* timer on */

    bit set mode1 IRPTEN;         { enable global int.}

    r1 = 0;         /* disable chaining */
    dm(CP0)=r1;                     /* receive block chain pt. */
    dm(CP2)=r1;                     /* transmit block chain pt. */
    dm(CP3)=r1;                     /* transmit block chain pt. */
    dm(CP1)=r1;                     /* receive block chain pt. */

/* disable all SPORTS */
    r1 = 0;
    dm(STCTL0)=r1;
    dm(SRCTL0)=r1;      /* write zeros first */
    dm(RDIV0)=r1;
    dm(TDIV0)=r1;

    dm(STCTL1)=r1;
    dm(SRCTL1)=r1;      /* write zeros first */
    dm(RDIV1)=r1;
    dm(TDIV1)=r1;

    r1 = 0;         /* disable companding */
    dm(MRCCS0)=r1;
    dm(MTCCS0)=r1;
    dm(MRCCS1)=r1;
    dm(MTCCS1)=r1;

/*      SPORT0 Multichannel enable setup       */
/*      RX: 0,1,2                       */
/*      TX: 0,1,2                       */

    r1=0x0007;
    dm(MTCS0)=r1;
    dm(MRCS0)=r1;

/*      SPORT0 Enabled                      */
/*      SLEN=(bits-1), SDEN enabled, SCHEN enabled.     */
/*      TX: MFD=1                                       */
/*      RX: MCE enabled, NCH=sport0_channels-1          */

    r1= 0x1c0000 | ((SPORT0_BITS-1) << 4);
    dm(STCTL0)=r1;
    r1 = 0x08c0000 \
         | ((SPORT0_CHANNELS-1) << 24) \
         | ((SPORT0_BITS-1) << 4);
    dm(SRCTL0)=r1;

    i4 = regs_1847;                 /* pointer to initial commands */
    r4 = @regs_1847;                /* number of commands */

    bit set imask SPT0I;  /* enable sport0 xmit irqs */

/* set up chaning */
    r1=xmit_tcb0;
    dm(CP2)=r1;                     /* transmit block chain pt. */
    r1=rcvr_tcb0;
    dm(CP0)=r1;                     /* receive block chain pt. */

    idle;
    r4 = pass r4;                   /* tickle zero flag */
    if ne jump (pc,-2);             /* wait for zero r4 to go to zero */

    idle;
    r0 = dm(rx_buf0);               /* get 1847 status word */
    btst r0 by 2;                   /* test bit 1 */
    if not sz jump (pc,-3);         /* wait for autocal to finish */

    idle;

    r0=0xbf3f;
    r1=dm(regs_1847+6);
    r1=r0 and r1;
    dm(tx_buf0)=r1;                  /* unmute left DAC      */

    idle;

    r1=dm(regs_1847+7);
    r0= r1 and r0;
    dm(tx_buf0)=r0;                  /* unmute right DAC     */

    idle;

    bit clr imask SPT0I;        /* no more tx irqs */

    bit clr mode1 IRPTEN;         { disable global int.}
    nop;

/* set up interupt alternate registers */
    bit set mode1 SRD1L|SRD1H|SRRFL|SRRFH; { use all secondary registers}
    nop;

    i0=_play_fifo;           { output to D/A pointer (playback) }
    b0=i0;
    i1=_play_fifo;           { another circular pointer }
    b1=i1;
    i2=0;           { circular pointer for sendout }
    b2=0;
    i3=_record_fifo;           { input from A/D pointer (record) }
    b3=i3;
    i4=_record_fifo;           { another circular pointer }
    b4=i4;
    i5=_record_fifo;           { another circular pointer }
    b5=i5;
    l0=FIFO_LENGTH;            { length for circular buffer }
    l1=FIFO_LENGTH;            { length for circular buffer }
    l2=FIFO_LENGTH;            { length for circular buffer }
    l3=FIFO_LENGTH;            { length for circular buffer }
    l4=FIFO_LENGTH;            { length for circular buffer }
    l5=FIFO_LENGTH;            { length for circular buffer }
    m1=1;                      { increment for sample buffer }
    r5=0xffff0000;             { and mask }

    bit clr mode1 SRD1L|SRD1H|SRRFL|SRRFH; { back to original registers}
    nop;

    bit set imask SPR0I;            /* allow sp0 rec. interrupts */

    exit;

.ENDSEG;