bucket.v

来自「MII接口1转2处理」· Verilog 代码 · 共 65 行

//bucket.v
//xikang
//2003-06-25
//

module bucket ( reset, clk, rate, usage, nocredit );
parameter	BITWIDTH = 18,
	 		DEPTH = 2 ** BITWIDTH - 1,
			BASIC = 2 ** 11 - 1;


input 	reset, clk, usage;
input [6 : 0] rate;
output reg nocredit;

reg		income, ts; 
reg [BITWIDTH - 1 : 0]	credit;
wire [BITWIDTH - 1 : 0]	mask;
reg [6 : 0]	cnt;

assign mask = BASIC;

always @ ( posedge clk, negedge reset )
begin
	if( ! reset )
	begin
		ts		<= 0;
		cnt		<= 0;
		credit 	<= BASIC;
		nocredit		<= 0;
		income	<= 0;
	end
	else 
	begin
		ts <= ~ ts;

		if( ts )
		begin
			if( cnt == 99 )
				cnt <= 0;
			else
				cnt <= cnt + 1;

			if( cnt == rate )
				income <= 0;
			else if( cnt == 0 )
				income <= 1;
		end

		if( ( income && ts ) && ( ! usage ) && ( credit != DEPTH ) )
			credit <= credit + 1;
		else if( ( ! ( income && ts )) && usage && ( credit != 0 ) )
			credit <= credit - 1;

		if( (( ~ mask ) & credit ) == 0 )
			nocredit <= 1;
		else
			nocredit <= 0;
	end
end
endmodule