myfifo.vhd

MII接口1转2处理

LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

LIBRARY lpm;
USE lpm.lpm_components.all;

ENTITY myfifo IS
	PORT
	(
		data		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
		wrreq		: IN STD_LOGIC ;
		rdreq		: IN STD_LOGIC ;
		clk			: IN STD_LOGIC ;
		aclr		: IN STD_LOGIC ;
		full		: out STD_LOGIC ;
		empty		: out STD_LOGIC ;
		usedw		: out STD_LOGIC_VECTOR( 4 downto 0 );
		q		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
	);
END myfifo;


ARCHITECTURE SYN OF myfifo IS

	COMPONENT fiforam
	PORT (
			rdclock	: IN STD_LOGIC ;
			wren	: IN STD_LOGIC ;
			wrclock	: IN STD_LOGIC ;
			q	: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
			rden	: IN STD_LOGIC ;
			data	: IN STD_LOGIC_VECTOR (7  DOWNTO 0);
			rdaddress	: IN STD_LOGIC_VECTOR (4 DOWNTO 0);
			wraddress	: IN STD_LOGIC_VECTOR (4 DOWNTO 0)
	);
	END COMPONENT;

signal rdaddr : std_logic_vector( 4 downto 0 );
signal wraddr : std_logic_vector( 4 downto 0 );
signal iusedw  : std_logic_vector( 4 downto 0 );
signal ifull : std_logic;
signal iempty : std_logic;

signal rden : std_logic;
signal wren : std_logic;

BEGIN

	full	<= ifull;
	empty	<= iempty;
	usedw	<= iusedw;

	iempty 	<= '1' when ( iusedw = "00000" ) else '0';
	ifull 	<= '1' when ( iusedw = "11111" ) else '0';
	rden 	<= rdreq and ( not iempty );
	wren 	<= wrreq and ( not ifull );

	process( clk, aclr )
	begin
		if( rising_edge( clk ) ) then
			if( rden = '1' ) and ( wren = '0' ) then
				iusedw <= iusedw - '1';
			elsif( wren = '1' ) and ( rden = '0' ) then
				iusedw <= iusedw + '1';
			end if;

			if( rden = '1' ) then
				rdaddr <= rdaddr + '1';
			end if;

			if( wren = '1' ) then
				wraddr <= wraddr + '1';
			end if;
		end if;
		
		if( aclr = '1' ) then
			wraddr <= ( others => '0' );
			rdaddr <= ( others => '0' );
			iusedw  <= ( others => '0' );
		end if;
	end process;

	U_FIFORAM : fiforam
	PORT MAP (
		rdclock => clk,
		wren => wren,
		wrclock => clk,
		rden => rden,
		data => data,
		rdaddress => rdaddr,
		wraddress => wraddr,
		q => q
	);

END SYN;