fiforam.vhd

MII接口1转2处理

LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

LIBRARY lpm;
USE lpm.lpm_components.all;

ENTITY fiforam IS
	PORT
	(
		rdclock	: IN STD_LOGIC ;
		wren	: IN STD_LOGIC ;
		wrclock	: IN STD_LOGIC ;
		q	: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
		rden	: IN STD_LOGIC ;
		data	: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
		rdaddress	: IN STD_LOGIC_VECTOR (4 DOWNTO 0);
		wraddress	: IN STD_LOGIC_VECTOR (4 DOWNTO 0)
	);
END fiforam;


ARCHITECTURE SYN OF fiforam IS

	COMPONENT lpm_ram_dp
	GENERIC (
		lpm_width		: NATURAL;
		lpm_widthad		: NATURAL;
		rden_used		: STRING;
		intended_device_family		: STRING;
		lpm_indata		: STRING;
		lpm_wraddress_control		: STRING;
		lpm_rdaddress_control		: STRING;
		lpm_outdata		: STRING;
		use_eab		: STRING;
		lpm_type		: STRING
	);
	PORT (
			rdclock	: IN STD_LOGIC ;
			wren	: IN STD_LOGIC ;
			wrclock	: IN STD_LOGIC ;
			q	: OUT STD_LOGIC_VECTOR (lpm_width - 1 DOWNTO 0);
			rden	: IN STD_LOGIC ;
			data	: IN STD_LOGIC_VECTOR (lpm_width - 1  DOWNTO 0);
			rdaddress	: IN STD_LOGIC_VECTOR (lpm_widthad - 1 DOWNTO 0);
			wraddress	: IN STD_LOGIC_VECTOR (lpm_widthad - 1 DOWNTO 0)
	);
	END COMPONENT;

begin

	lpm_ram_dp_component : lpm_ram_dp
	GENERIC MAP (
		lpm_width => 8,
		lpm_widthad => 5,
		rden_used => "TRUE",
		intended_device_family => "UNUSED",
		lpm_indata => "REGISTERED",
		lpm_wraddress_control => "REGISTERED",
		lpm_rdaddress_control => "REGISTERED",
		lpm_outdata => "UNREGISTERED",
		use_eab => "ON",
		lpm_type => "LPM_RAM_DP"
	)
	PORT MAP (
		rdclock => rdclock,
		wren => wren,
		wrclock => wrclock,
		rden => rden,
		data => data,
		rdaddress => rdaddress,
		wraddress => wraddress,
		q => q
	);

END SYN;