📄 btscriptgen.c
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//
void scriptWriteCode(UInt32 address, UInt32 *data, UInt32 count)
{
if (!this.fileOutputAsText)
{
address &= ~3 ;
address |= 1 ;
scriptWord(address);
scriptWord(count);
while (count-- != 0)
{
scriptByte((UInt8)((*data >> 0) & 0xff)) ;
scriptByte((UInt8)((*data >> 8) & 0xff)) ;
scriptByte((UInt8)((*data >> 16) & 0xff)) ;
scriptByte((UInt8)((*data >> 24) & 0xff)) ;
data++ ;
}
}
else
{
fprintf(scriptFile, "\nwritelist %08X %08X // Address 0x%08X, words %d\n",address, count,address, count);
while (count-- != 0)
{
fprintf(scriptFile, " %08X\n",*data);
data++ ;
}
fprintf(scriptFile, "\n");
}
}
//-----------------------------------------------------------------------------
// FUNCTION: scriptComment
//
// DESCRIPTION: Output comments to the boot script
//
// RETURN: None
//
// NOTES:
//
//-----------------------------------------------------------------------------
//
static void scriptComment(char *text)
{
if (!this.fileOutputAsText)
{
//do noting
}
else
{
fprintf(scriptFile, "// %s\n",text);
}
}
//-----------------------------------------------------------------------------
// FUNCTION: scriptByte
//
// DESCRIPTION: Output 1 byte to the boot script
//
// RETURN: None
//
// NOTES:
//
//-----------------------------------------------------------------------------
//
static void scriptByte(UInt8 data)
{
if (!this.fileOutputAsText)
{
fwrite(&data, 1, 1, scriptFile);
scriptBytes++ ;
}
}
//-----------------------------------------------------------------------------
// FUNCTION: scriptWord
//
// DESCRIPTION: Output 4 bytes to the boot script
//
// RETURN: None
//
// NOTES:
//
//-----------------------------------------------------------------------------
//
static void scriptWord(UInt32 data)
{
scriptByte((UInt8)((data >> 0) & 0xff)) ;
scriptByte((UInt8)((data >> 8) & 0xff)) ;
scriptByte((UInt8)((data >> 16) & 0xff)) ;
scriptByte((UInt8)((data >> 24) & 0xff)) ;
}
//-----------------------------------------------------------------------------
// FUNCTION: scriptWriteSingle
//
// DESCRIPTION: Command for boot script to write a single word
//
// RETURN: None
//
// NOTES:
//
//-----------------------------------------------------------------------------
//
static void scriptWriteSingle(UInt32 address, UInt32 data)
{
if (!this.fileOutputAsText)
{
address &= ~3 ;
scriptWord(address);
scriptWord(data);
}
else
{
fprintf(scriptFile, "write %08X %08X 0\n",address,data);
}
}
//-----------------------------------------------------------------------------
// FUNCTION: scriptDelay
//
// DESCRIPTION: Command for boot script to delay
//
// RETURN: None
//
// NOTES:
//
//-----------------------------------------------------------------------------
//
static void scriptDelayCycles(UInt32 cycles)
{
if (!this.fileOutputAsText)
{
scriptWord((cycles << 4) | 0x2);
}
else
{
fprintf(scriptFile, "\ndelay %08X\n\n",cycles);
}
}
//-----------------------------------------------------------------------------
// FUNCTION: scriptDelaySeconds
//
// DESCRIPTION: Command for boot script to delay by seconds
//
// RETURN: None
//
// NOTES:
//
//-----------------------------------------------------------------------------
//
static void scriptDelaySeconds(float seconds) {
UInt32 cycles ;
cycles = (UInt32) ((seconds * 27.0e+6) + 0.5) ;
scriptDelayCycles(cycles) ;
}
//-----------------------------------------------------------------------------
// FUNCTION: writeMacAddress
//
// DESCRIPTION: write Mac address in boot script
//
// RETURN: None
//
// NOTES:
//
//-----------------------------------------------------------------------------
//
static void writeMacAddress(UInt8 *mac_address, UInt32 mmio_base)
{
UInt32 aa, bb, cc;
// Setup MAC address (default 00:50:c2:19:50:7b)
// These eeprom locations must be changed to a
// unique MAC address for each board
scriptComment("Set MAC address");
aa = (mac_address[5]<<8 | mac_address[4]);
bb = (mac_address[3]<<8 | mac_address[2]);
cc = (mac_address[1]<<8 | mac_address[0]);
scriptWriteSingle(mmio_base+EMAC_SA0, aa) ;
scriptWriteSingle(mmio_base+EMAC_SA1, bb) ;
scriptWriteSingle(mmio_base+EMAC_SA2, cc) ;
}
//-----------------------------------------------------------------------------
// FUNCTION: writeClocks
//
// DESCRIPTION: write Clock settings in boot script
//
// RETURN: None
//
// NOTES:
//
//-----------------------------------------------------------------------------
//
static void writeClocks(UInt32 cpu_speed, UInt32 ddr_speed, UInt32 mmio_base)
{
// Work-around for hardware problem 3594 CLOCKS -- Internal clock dividers need to be initialized.
// This needs to be done as one of the first things in the script -- at least before the mmio clock
// gets switched. If done too late, it will hang things up (it won't work):
scriptComment("Initialize Clock diverder in CAB block");
scriptComment("Work-around for hardware problem 3594 CLOCKS");
scriptWriteSingle(mmio_base+CAB_DIV_PD, mPd_192 |
mPd_173 |
mPd_157 |
mPd_144 |
mPd_133 |
mPd_123 |
mPd_115 |
mPd_108 |
mPd_102);
scriptWriteSingle(mmio_base+CAB_DIV_PD, mPu_AllClks);
// Setup PLL2 for DDR speed:
scriptComment("Set DDR speed using PLL2");
scriptWriteSingle(mmio_base+PLL2_CTL, (FindPllFrequency(ddr_speed) & 0xFFFFFFF2 )); // To insure backwards compability pll_p & pll_bp must be masked.
// Setup PLL0 for CPU Speed:
scriptComment("Set CPU speed using PLL0");
scriptWriteSingle(mmio_base+PLL0_CTL, FindPllFrequency(cpu_speed) );
scriptDelayCycles(0x3000) ; // Wait 300 us -> Turn ON/OFF logic.
// enable and select tm3260 clock, stretch ON
// 00000003
// enable and select tm3260 clock, stretch OFF
// 00000013
scriptComment("Set clock sources");
scriptWriteSingle(mmio_base+CLK_TM_CTL, mTm_stretch_n | // Enable and select tm3260 clock, stretch OFF.
mSel_clk_tm_stretch_n |
mEn_clk_tm );
scriptWriteSingle(mmio_base+CLK_MEM_CTL, mSel_clk_mem_PLL2 | // enable and select ddr clock
mEn_clk_mem );
scriptWriteSingle(mmio_base+CLK_MMIO_CTL, //m144_clk_dtl_mmio_src | // mkl -- 144 clock does not work with USB JTAG
m102_clk_dtl_mmio_src | // change to 102 clock.
mClk_dtl_mmio_src | // enable and select MMIO clock
mEn_dtl_mmio );
scriptWriteSingle(mmio_base+CLK_PCI_CTL, mSel_clk_pci_27MHz | // enable and select PCI clock
mEn_clk_pci );
scriptDelayCycles(0x3000) ; // Wait 300 us -> Turn ON/OFF logic.
//
// Program the DDR controller
//
scriptComment("Program the DDR controller");
scriptWriteSingle(mmio_base+DDR_DEF_BANK_SWITCH, mBANK_SWITCH) ; // Switch banks every 2^BANK_SWITCH columns.
// DDR_MR: CAS == 3.0 : mCAS_latency_3
// DDR_MR: CAS == 2.5 : mCAS_latency_6
// DDR_MR: CAS == 2.0 : mCAS_latency_2
scriptWriteSingle(mmio_base+DDR_MR, mDDR_mode_resetDLL | //normal operation/reset DLL)
mCAS_latency_3 | //CAS latency
mDDR_burst3 ); //burst length
// DDR_EMR
scriptWriteSingle(mmio_base+DDR_EMR,0) ;
// DDR_PRECHARGE_BIT: bit 8 for x32 devices,
// DDR_PRECHARGE_BIT: bit 10 for x16 devices.
scriptWriteSingle(mmio_base+DDR_PRECHARGE_BIT, 10) ;
// DDR_ROW_WIDTH: 12 bits: 128 Mbit in x16.
// DDR_ROW_WIDTH: 13 bits: 256 Mbit in x16.
scriptWriteSingle(mmio_base+RANK0_ROW_WIDTH, mROW_WIDTH_8k) ;
// DDR_COLUMN_WIDTH: 9 bits: 128 Mbit in x16.
// DDR_COLUMN_WIDTH: 9 bits: 256 Mbit in x16.
scriptWriteSingle(mmio_base+RANK0_COLUMN_WIDTH, mCOLUMN_WIDTH_1k) ;
//scriptWriteSingle(mmio_base+RANK0_COLUMN_WIDTH, mCOLUMN_WIDTH_512) ;
scriptWriteSingle(mmio_base+DDR_TRCD, mTRCD_WR_3t | //Minimum time between active and write command.
mTRCD_RD_3t); //Minimum time between active and read command.
scriptWriteSingle(mmio_base+DDR_TRC, mTRC_12) ; //Minimum time between two active commands to the same bank.
scriptWriteSingle(mmio_base+DDR_TWTR, mTWTR_2) ; //Write to read command delay.
scriptWriteSingle(mmio_base+DDR_TWR, mTWR_3) ; //Write recovery time.
scriptWriteSingle(mmio_base+DDR_TRP, mTRP_4) ; //Precharge command period.
scriptWriteSingle(mmio_base+DDR_TRAS, mTRAS_8) ; //Minimum delay from active to precharge.
scriptWriteSingle(mmio_base+DDR_TRRD, mTRRD_2) ; //Active bank a to active bank b command.
scriptWriteSingle(mmio_base+DDR_TRFC, mTRFC_14) ; //Auto refresh command period.
scriptWriteSingle(mmio_base+DDR_TMRD, mTMRD_2) ; //Load mode register command cycle time.
// DDR_TCAS: CAS == 3.0 : TCAS_6
// DDR_TCAS: CAS == 2.5 : TCAS_5
// DDR_TCAS: CAS == 2.0 : TCAS_4
scriptWriteSingle(mmio_base+DDR_TCAS, mTCAS_6) ; //CAS read latency, specified in halve cycles.
scriptWriteSingle(mmio_base+DDR_RF_PERIOD, mRF_7uPER_200Mhz) ; //Refresh period expressed in terms of cycles.
// 32-bit interface in x32
// DDR_CTL: 00000001
// 32-bit interace in x16
// DDR_CTL: 00000009
// 16-bit interface in x16
// DDR_CTL: 0000000d
scriptWriteSingle(mmio_base+IP_2031_CTL,mWARM_START); //Warm Start of DDR controller.
scriptWriteSingle(mmio_base+IP_2031_CTL, mDDR_DQS_PER_BYTE | //A separate 揹qs⌨️ 快捷键说明
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