📄 btscriptgen.c
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scriptWriteSingle(mmio_base + TM32_DRAM_HI, sdram_limit); // TM32_DRAM_HI
scriptWriteSingle(mmio_base + TM32_DRAM_CLIMIT, cacheable_limit); // TM32_DRAM_CLIMIT
scriptWriteSingle(mmio_base + TM32_START_ADDR, uBTM_start); // TM32_START_ADDR
// Used for debugging the boot stages. Pre DMA load value.
scriptWriteSingle(mmio_base + TM_DBG_N_DATA_OUT, 0x76543210) ; // Write identifiable value to TM_DBG_1_DATA_OUT for debugging.
// Deassert SYS_RSTN_OUT_N so we can talk to NOR flash
scriptWriteSingle(mmio_base + RST_CTL, mREL_SYS_RST_OUT) ; // Negate SYS_RSTN_OUT_N
scriptComment("Setup XIO Profile");
//XIO profile setup -- using values from structure
for (i=0; i < MAX_XIO_PROFILES; i++)
{
if (this.profile[i] != 0)
{
scriptWriteSingle( mmio_base + xioProfOfset[i], this.profile[i]);
//find memory address of nor in XIO
if ( (this.profile[i] & 0x00000018) == 0x00000008) //0x08 is nor type device
{
// calculate offset in 8MB offsets and set it as source address of DMA
flashStart = (xio_base + ( (this.profile[i] & 0x000001E0 ) * 0x00040000));
}
}
}
//----------------------------------------------------------------
// Use DMA to Load code from NOR FLASH into SDRAM
//----------------------------------------------------------------
scriptComment("Setup DMA address");
// Set source address of DMA to code in flash
scriptWriteSingle( mmio_base + dma_eaddr, flashStart);
// Set destination address in memory
// Must match what uBTM was linked to start at (TM32_START_ADDR)
scriptWriteSingle( mmio_base + dma_iaddr, uBTM_start);
// Set length in words, we're grabbing 8K bytes or 0x2000 words
scriptWriteSingle( mmio_base + dma_length, 0x2000);
scriptWriteSingle(default_base+dma_ctrl, mSnd2xio | //1 = DMA will target XIO.
mMax_burst_size_128 | //128 data phase size PCI transaction.
mInit_dma | //Initiate DMA transaction.
mCmd_StartDMA ); //Start the DMA.
// Delay, for 16-bit NOR 8K fetch it takes 0x7800 periods
// Let's wait longer in 8 bit mode
scriptDelayCycles(0x30000) ;
// This provides a clean reset signal to the external peripherals.
scriptWriteSingle(mmio_base + RST_CTL, mASSERT_SYS_RST_OUT) ; // Assert SYS_RSTN_OUT_N
scriptDelayCycles(300000) ;
scriptWriteSingle(mmio_base + RST_CTL, mREL_SYS_RST_OUT) ; // Negate SYS_RSTN_OUT_N
// scriptDelayCycles(300000) ;
// Used for debugging the boot stages. Post DMA load value.
scriptWriteSingle(mmio_base + TM_DBG_N_DATA_OUT, 0x00ABCDEF) ; // Write identifiable value to TM_DBG_1_DATA_OUT for debugging.
// Start TM32
scriptWriteSingle(mmio_base + TM32_CTL, mTM32_Start); // TM32_CTL: start
scriptWord(0x6) ; // to terminate boot script
fclose(scriptFile);
printf("NOR bootscript write complete. Script size: %5d bytes\n\n", scriptBytes) ;
return 0;
} // End of writeNorScript()
//-----------------------------------------------------------------------------
// FUNCTION: writeNandScript
//
// DESCRIPTION: opens and writes nand script file
//
// RETURN: 0 if successful or ERR_NANDSCRIPT_WRITE in case of an error.
//
// NOTES:
//
//-----------------------------------------------------------------------------
//
static int writeNandScript( char *file_name, UInt32 sdram_base, UInt32 sdram_limit, UInt32 cacheable_limit,
UInt32 uBTM_start, UInt32 xio_base, UInt32 mmio_base,
UInt32 cpu_speed, UInt32 ddr_speed, UInt8 *mac_address)
{
UInt32 i;
UInt32 aa, bb, cc;
UInt32 flashStart;
UInt32 size = 8 * 1024; // Total size of code we want to move
UInt32 incr = 512; // One page
// registers are not placed consequtive!!!! Therefore this strange construction.
UInt32 xioProfOfset[MAX_XIO_PROFILES] = {xio_sel0_prof,
xio_sel1_prof,
xio_sel2_prof,
xio_sel3_prof,
xio_sel4_prof};
// open file for writing ...
if ((scriptFile = fopen(file_name, "wb")) == NULL)
{
fprintf(stderr, "unable to open script file %s for write\n", file_name);
return ERR_NANDSCRIPT_WRITE;
}
scriptBytes = 0 ;
// The "script" functions below specify commands to be
// executed in this boot script.
// You can edit these to customize the boot script
// Dummy byte for <= 2KB eeproms
scriptByte(0) ;
scriptComment(g_btscriptText);
writeMacAddress(mac_address, default_base) ;
writeClocks(cpu_speed, ddr_speed, default_base) ;
setupPCI(sdram_limit, default_base, PCI_MASTER) ;
scriptWriteSingle(default_base+base10, sdram_base) ; // pci base 0
scriptWriteSingle(default_base+base14, mmio_base) ; // pci base 1
scriptDelayCycles(50) ; // Wait for bus controller to stabilize.
// MMIO base has changed, so use new base value plus offset from now on:
//Note: If XIO base is 1c000000 apperture size should not exceed 64 MB. scriptWriteSingle(mmio_base + base18, xio_base) ; // pci base 2
scriptWriteSingle(mmio_base + base18, xio_base) ; // pci base 2
scriptWriteSingle(mmio_base + subsystem_ids, this.board_id); // Sub-system and vendor ID - Enables PCI
// Set the upper 8-bits of the 16-bit XIO data to be primary function instead of default GPIO
// to enable Flash access:
scriptWriteSingle(mmio_base + GPIO_CTL1, mPRI_FunctionMode << 30 | // primary function mode for GPIO 31
mPRI_FunctionMode << 28 | // primary function mode for GPIO 30
mPRI_FunctionMode << 26 | // primary function mode for GPIO 29
mPRI_FunctionMode << 24 | // primary function mode for GPIO 28
mPRI_FunctionMode << 22 | // primary function mode for GPIO 27
mPRI_FunctionMode << 20 | // primary function mode for GPIO 26
mRetainCurrentMode << 18 | // retain current GPIO Mode for GPIO 25
mRetainCurrentMode << 16 | // retain current GPIO Mode for GPIO 24
mRetainCurrentMode << 14 | // retain current GPIO Mode for GPIO 23
mRetainCurrentMode << 12 | // retain current GPIO Mode for GPIO 22
mRetainCurrentMode << 10 | // retain current GPIO Mode for GPIO 21
mRetainCurrentMode << 8 | // retain current GPIO Mode for GPIO 20
mRetainCurrentMode << 6 | // retain current GPIO Mode for GPIO 19
mRetainCurrentMode << 4 | // retain current GPIO Mode for GPIO 18
mRetainCurrentMode << 2 | // retain current GPIO Mode for GPIO 17
mRetainCurrentMode << 0 ); // retain current GPIO Mode for GPIO 16
scriptWriteSingle(mmio_base + GPIO_CTL2, mRetainCurrentMode << 30 | // retain current GPIO Mode for GPIO 47
mRetainCurrentMode << 28 | // retain current GPIO Mode for GPIO 46
mRetainCurrentMode << 26 | // retain current GPIO Mode for GPIO 45
mRetainCurrentMode << 24 | // retain current GPIO Mode for GPIO 44
mRetainCurrentMode << 22 | // retain current GPIO Mode for GPIO 43
mRetainCurrentMode << 20 | // retain current GPIO Mode for GPIO 42
mRetainCurrentMode << 18 | // retain current GPIO Mode for GPIO 41
mRetainCurrentMode << 16 | // retain current GPIO Mode for GPIO 40
mRetainCurrentMode << 14 | // retain current GPIO Mode for GPIO 39
mRetainCurrentMode << 12 | // retain current GPIO Mode for GPIO 38
mRetainCurrentMode << 10 | // retain current GPIO Mode for GPIO 37
mPRI_FunctionMode << 8 | // primary function Mode for GPIO 36
mPRI_FunctionMode << 6 | // primary function Mode for GPIO 35
mPRI_FunctionMode << 4 | // primary function Mode for GPIO 34
mPRI_FunctionMode << 2 | // primary function Mode for GPIO 33
mPRI_FunctionMode << 0 ); // primary function Mode for GPIO 32
// stop tm32 core
scriptWriteSingle(mmio_base + TM32_CTL, mTM32_Stop); // TM32_CTL: stop
// DCS SDRAM mapping
scriptWriteSingle(mmio_base + APERTURE_WE, mDCS_DRAM_WE); // DCS_DRAM_WE: write enabled
scriptWriteSingle(mmio_base + DCS_DRAM_LO, sdram_base); // DCS_DRAM_LO
scriptWriteSingle(mmio_base + APERTURE_WE, mDCS_DRAM_WE); // DCS_DRAM_WE: write enabled
scriptWriteSingle(mmio_base + DCS_DRAM_HI, sdram_limit); // DCS_DRAM_HI
// TM SDRAM mapping
scriptWriteSingle(mmio_base + TM32_DRAM_LO, sdram_base); // TM32_DRAM_LO
scriptWriteSingle(mmio_base + TM32_DRAM_HI, sdram_limit); // TM32_DRAM_HI
scriptWriteSingle(mmio_base + TM32_DRAM_CLIMIT, cacheable_limit); // TM32_DRAM_CLIMIT
scriptWriteSingle(mmio_base + TM32_START_ADDR, uBTM_start); // TM32_START_ADDR
// Used for debugging the boot stages. Pre DMA load value.
scriptWriteSingle(mmio_base + TM_DBG_N_DATA_OUT, 0x76543210) ; // Write identifiable value to TM_DBG_1_DATA_OUT for debugging.
// Deassert SYS_RSTN_OUT_N so we can talk to flash
//scriptWriteSingle(mmio_base + RST_CTL, mREL_SYS_RST_OUT) ; // Negate SYS_RSTN_OUT_N
scriptComment("Setup XIO Profile");
//XIO profile setup -- using values from structure
for (i=0; i < MAX_XIO_PROFILES; i++)
{
if (this.profile[i] != 0)
{
scriptWriteSingle( mmio_base + xioProfOfset[i], this.profile[i]);
//find memory address of nand in XIO
//if ( (this.profile[i] & 0x00000018) == 0x00000008) //0x08 is nor type device
if ( (this.profile[i] & 0x00000018) == 0x00000010) //0x10 is nand type device
{
// calculate offset in 8MB offsets and set it as source address of DMA
flashStart = (xio_base + ( (this.profile[i] & 0x000001E0 ) * 0x00040000));
}
}
}
//----------------------------------------------------------------
// Use DMA to Load code from NAND FLASH into SDRAM
//----------------------------------------------------------------
scriptComment("Setup DMA address");
for (i = 0; i < size/incr; i++)
{
// Set source address of DMA to code in flash
scriptWriteSingle( mmio_base + dma_eaddr, flashStart); // block 1 in NAND
// Set destination address in memory
scriptWriteSingle( mmio_base + dma_iaddr, uBTM_start); // Must match where uBTM was linked to.
// Set length in words, we're grabbing 8K bytes or 0x2000 words
scriptWriteSingle( mmio_base + dma_length, incr/4); // 512 bytes (128 * 4-byte words)
// Start the DMA
scriptWriteSingle(default_base+dma_ctrl, mSnd2xio | //1 = DMA will target XIO.
mMax_burst_size_128 | //128 data phase size PCI transaction.
mInit_dma | //Initiate DMA transaction.
mCmd_StartDMA ); //Start the DMA.
scriptDelayCycles(0x1000) ; // wait a long time
flashStart += incr;
uBTM_start += incr;
}
// This provides a clean reset signal to the external peripherals.
// scriptDelayCycles(300000) ;
// scriptWriteSingle(mmio_base + RST_CTL, mASSERT_SYS_RST_OUT) ; // Assert SYS_RSTN_OUT_N
// scriptDelayCycles(300000) ;
scriptWriteSingle(mmio_base + RST_CTL, mREL_SYS_RST_OUT) ; // Negate SYS_RSTN_OUT_N
// Used for debugging the boot stages. Post DMA load value.
scriptWriteSingle(mmio_base + TM_DBG_N_DATA_OUT, 0x00ABCDEF) ; // Write identifiable value to TM_DBG_1_DATA_OUT for debugging.
// Start TM32
scriptWriteSingle(mmio_base + TM32_CTL, mTM32_Start); // TM32_CTL: start
scriptWord(0x6) ; // to terminate boot script
fclose(scriptFile);
printf("Nand bootscript write complete. Script size: %5d bytes\n\n", scriptBytes) ;
return 0;
} // End of writeNandScript()
//-----------------------------------------------------------------------------
// FUNCTION: read_file
//
// DESCRIPTION: Read a file into a buffer in memory
//
// RETURN: The number of bytes read from the file
//
// NOTES:
//
//-----------------------------------------------------------------------------
//
static int read_file(UInt8 *buffer, char *filename)
{
int L1fd, n, nbytes;
struct stat file_stat;
if ((L1fd = open(filename, O_RDONLY|O_BINARY)) == -1) {
fprintf(stderr, "\tUnable to open file: %s\n", filename);
fprintf(stderr, "\tFile doesn't exist or not readable\n");
return 0;
}
if (fstat(L1fd, &file_stat)) {
fprintf(stderr, "tUnable to fstat file: %s\n", filename);
return 0;
}
nbytes = (unsigned long)file_stat.st_size;
if (nbytes > MAX_EEPROM_SIZE) {
fprintf(stderr, "\tFile has %5d bytes. must be less than %5d bytes\n",
nbytes, MAX_EEPROM_SIZE);
return 0;
}
n = read(L1fd, buffer, nbytes) ;
if (n != nbytes) {
fprintf(stderr, "\tUnable to read %d bytes, actually read %d bytes, error no: %d\n",
nbytes, n, errno);
return 0;
}
close(L1fd);
printf("\tJTAG Program size: %5d bytes read from disk.\n", nbytes);
return nbytes;
}
//-----------------------------------------------------------------------------
// FUNCTION: scriptWriteCode
//
// DESCRIPTION: Command for boot script to write multiple words
//
// RETURN: None
//
// NOTES:
//
//-----------------------------------------------------------------------------
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