📄 btscriptgen.c
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//-----------------------------------------------------------------------------
// Functions:
//-----------------------------------------------------------------------------
//
//-----------------------------------------------------------------------------
// FUNCTION: writeHostScript
//
// DESCRIPTION: opens and writes hosted script file
//
// RETURN: 0 if successful or ERR_HOSTSCRIPT_WRITE in case of an error.
//
// NOTES:
//
//-----------------------------------------------------------------------------
//
static int writeHostScript( char *file_name, UInt32 sdram_base, UInt32 sdram_limit, UInt32 cacheable_limit,
UInt32 uBTM_start, UInt32 xio_base, UInt32 mmio_base,
UInt32 cpu_speed, UInt32 ddr_speed, UInt8 *mac_address)
{
// open file for writing ...
if ((scriptFile = fopen(file_name, "wb")) == NULL)
{
fprintf(stderr, "unable to open script file %s for write\n", file_name);
return ERR_HOSTSCRIPT_WRITE;
}
scriptBytes = 0 ;
scriptComment(g_btscriptText);
// The "script" functions below specify commands to be
// executed in this boot script.
// You can edit these to customize the boot script
// Dummy byte for <= 2KB eeproms
scriptByte(0) ;
//----------------------------------------------------------------
// Setup MAC address (default 00:50:c2:19:50:7b)
// These eeprom locations must be changed to a unique MAC address for each board,
// usually using the jpgmLcp program, or by poking directly with an eeprom programmer.
// The jpgmLcp program looks for these in a fixed offset within the eeprom and updates
// them, so don't move this writeMacAddress() function to anywhere else (it must be the
// first thing in the eeprom, after the dummy zero byte, if present):
writeMacAddress(mac_address, default_base) ;
writeClocks(cpu_speed, ddr_speed, default_base) ;
setupPCI(sdram_limit, default_base, PCI_HOST) ;
scriptWriteSingle(default_base+subsystem_ids, this.board_id); // Sub-system and vendor ID - Enables PCI
scriptWord(0x6) ; // to terminate boot script
fclose(scriptFile);
printf("HOST bootscript write complete. Script size: %5d bytes\n", scriptBytes) ;
return 0;
} // end of host eeprom write
//-----------------------------------------------------------------------------
// FUNCTION: writeJTAGScript
//
// DESCRIPTION: opens and writes jtag script file
//
// RETURN: 0 if successful or ERR_JTAGSCRIPT_WRITE in case of an error.
//
// NOTES:
//
//-----------------------------------------------------------------------------
//
static int writeJTAGScript( char *file_name, UInt32 sdram_base, UInt32 sdram_limit, UInt32 cacheable_limit,
UInt32 uBTM_start, UInt32 xio_base, UInt32 mmio_base,
UInt32 cpu_speed, UInt32 ddr_speed, UInt8 *mac_address, char *mi_file_name)
{
UInt32 aa, bb, cc;
int file_size;
/* read input file */
file_size = read_file((UInt8 *) ibuffer, mi_file_name);
if (file_size == 0) {
printf("\t !!ERROR Cannot create JTAG boot script\n");
return ERR_JTAGSCRIPT_WRITE;
}
// open file for writing ...
if ((scriptFile = fopen(file_name, "wb")) == NULL)
{
fprintf(stderr, "unable to open script file %s for write\n", file_name);
return ERR_JTAGSCRIPT_WRITE;
}
scriptBytes = 0;
// The "script" functions below specify commands to be
// executed in this boot script.
// You can edit these to customize the boot script
// Dummy byte for <= 2KB eeproms
scriptByte(0);
scriptComment(g_btscriptText);
writeMacAddress(mac_address, default_base) ;
writeClocks(cpu_speed, ddr_speed, default_base) ;
setupPCI(sdram_limit, default_base, PCI_MASTER) ;
scriptWriteSingle(default_base+base10, sdram_base) ; // pci base 0
scriptWriteSingle(default_base+base14, mmio_base) ; // pci base 1
scriptDelayCycles(50) ; // Wait for bus controller to stabilize.
// MMIO base has changed, so use new base value plus offset from now on:
scriptWriteSingle(mmio_base + base18, xio_base) ; // pci base 2
scriptWriteSingle(mmio_base + subsystem_ids, this.board_id); // Sub-system and vendor ID - Enables PCI
// Set the upper 8-bits of the 16-bit XIO data to be primary function instead of default GPIO
// to enable Flash access:
scriptWriteSingle(mmio_base + GPIO_CTL1, mPRI_FunctionMode << 30 | // primary function mode for GPIO 31
mPRI_FunctionMode << 28 | // primary function mode for GPIO 30
mPRI_FunctionMode << 26 | // primary function mode for GPIO 29
mPRI_FunctionMode << 24 | // primary function mode for GPIO 28
mPRI_FunctionMode << 22 | // primary function mode for GPIO 27
mPRI_FunctionMode << 20 | // primary function mode for GPIO 26
mRetainCurrentMode << 18 | // retain current GPIO Mode for GPIO 25
mRetainCurrentMode << 16 | // retain current GPIO Mode for GPIO 24
mRetainCurrentMode << 14 | // retain current GPIO Mode for GPIO 23
mRetainCurrentMode << 12 | // retain current GPIO Mode for GPIO 22
mRetainCurrentMode << 10 | // retain current GPIO Mode for GPIO 21
mRetainCurrentMode << 8 | // retain current GPIO Mode for GPIO 20
mRetainCurrentMode << 6 | // retain current GPIO Mode for GPIO 19
mRetainCurrentMode << 4 | // retain current GPIO Mode for GPIO 18
mRetainCurrentMode << 2 | // retain current GPIO Mode for GPIO 17
mRetainCurrentMode << 0 ); // retain current GPIO Mode for GPIO 16
scriptWriteSingle(mmio_base + GPIO_CTL2, mRetainCurrentMode << 30 | // retain current GPIO Mode for GPIO 47
mRetainCurrentMode << 28 | // retain current GPIO Mode for GPIO 46
mRetainCurrentMode << 26 | // retain current GPIO Mode for GPIO 45
mRetainCurrentMode << 24 | // retain current GPIO Mode for GPIO 44
mRetainCurrentMode << 22 | // retain current GPIO Mode for GPIO 43
mRetainCurrentMode << 20 | // retain current GPIO Mode for GPIO 42
mRetainCurrentMode << 18 | // retain current GPIO Mode for GPIO 41
mRetainCurrentMode << 16 | // retain current GPIO Mode for GPIO 40
mRetainCurrentMode << 14 | // retain current GPIO Mode for GPIO 39
mRetainCurrentMode << 12 | // retain current GPIO Mode for GPIO 38
mRetainCurrentMode << 10 | // retain current GPIO Mode for GPIO 37
mPRI_FunctionMode << 8 | // primary function Mode for GPIO 36
mPRI_FunctionMode << 6 | // primary function Mode for GPIO 35
mPRI_FunctionMode << 4 | // primary function Mode for GPIO 34
mPRI_FunctionMode << 2 | // primary function Mode for GPIO 33
mPRI_FunctionMode << 0 ); // primary function Mode for GPIO 32
// stop tm32 core
scriptWriteSingle(mmio_base + TM32_CTL, mTM32_Stop); // TM32_CTL: stop and reset TM3260.
// DCS SDRAM mapping
scriptWriteSingle(mmio_base + APERTURE_WE, mDCS_DRAM_WE); // DCS_DRAM_WE: write enabled
scriptWriteSingle(mmio_base + DCS_DRAM_LO, sdram_base); // DCS_DRAM_LO
scriptWriteSingle(mmio_base + APERTURE_WE, mDCS_DRAM_WE); // DCS_DRAM_WE: write enabled
scriptWriteSingle(mmio_base + DCS_DRAM_HI, sdram_limit); // DCS_DRAM_HI
// TM SDRAM mapping
scriptWriteSingle(mmio_base + TM32_DRAM_LO, sdram_base); // TM32_DRAM_LO
scriptWriteSingle(mmio_base + TM32_DRAM_HI, sdram_limit); // TM32_DRAM_HI
scriptWriteSingle(mmio_base + TM32_DRAM_CLIMIT, cacheable_limit); // TM32_DRAM_CLIMIT
//TODO ram base address is assumed a start address of jtag loader app. Does not need to be!
scriptWriteSingle(mmio_base + TM32_START_ADDR, sdram_base); // TM32_START_ADDR
// Used for debugging the boot stages. Pre sdram load value.
scriptWriteSingle(mmio_base + TM_DBG_N_DATA_OUT, 0x76543210) ; // Write identifiable value to TM_DBG_1_DATA_OUT for debugging
// Load code into sdram
scriptWriteCode(sdram_base, ibuffer, (file_size+3)/4) ;
// This provides a clean reset signal to the external peripherals.
// So as to enable I2C access to registers using URD, for jtag boot:
//scriptWriteSingle(mmio_base + RST_CTL, mASSERT_SYS_RST_OUT) ; // Assert SYS_RSTN_OUT_N
//scriptDelayCycles(300000) ;
scriptWriteSingle(mmio_base + RST_CTL, mREL_SYS_RST_OUT) ; // Negate SYS_RSTN_OUT_N
//scriptDelayCycles(300000) ;
// Start TM32
scriptWriteSingle(mmio_base + TM32_CTL, mTM32_Start); // TM32_CTL: start
scriptWord(0x6) ; // to terminate boot script
fclose(scriptFile);
printf("JTAG bootscript write complete. Script size: %5d bytes\n", scriptBytes) ;
return 0;
} // End of writeJTAGScript().
//-----------------------------------------------------------------------------
// FUNCTION: writeNorScript
//
// DESCRIPTION: opens and writes nor script file
//
// RETURN: 0 if successful or ERR_NORSCRIPT_WRITE in case of an error.
//
// NOTES:
//
//-----------------------------------------------------------------------------
//
static int writeNorScript( char *file_name, UInt32 sdram_base, UInt32 sdram_limit, UInt32 cacheable_limit,
UInt32 uBTM_start, UInt32 xio_base, UInt32 mmio_base,
UInt32 cpu_speed, UInt32 ddr_speed, UInt8 *mac_address)
{
UInt32 i;
UInt32 aa, bb, cc;
UInt32 flashStart;
// registers are not placed consequtive!!!! Therefore this strange construction.
UInt32 xioProfOfset[MAX_XIO_PROFILES] = {xio_sel0_prof,
xio_sel1_prof,
xio_sel2_prof,
xio_sel3_prof,
xio_sel4_prof};
// open file for writing ...
if ((scriptFile = fopen(file_name, "wb")) == NULL)
{
fprintf(stderr, "unable to open script file %s for write\n", file_name);
return ERR_NORSCRIPT_WRITE;
}
scriptBytes = 0 ;
// The "script" functions below specify commands to be
// executed in this boot script.
// You can edit these to customize the boot script
// Dummy byte for <= 2KB eeproms
scriptByte(0) ;
scriptComment(g_btscriptText);
writeMacAddress(mac_address, default_base) ;
writeClocks(cpu_speed, ddr_speed, default_base) ;
setupPCI(sdram_limit, default_base, PCI_MASTER) ;
scriptWriteSingle(default_base+base10, sdram_base) ; // pci base 0
scriptWriteSingle(default_base+base14, mmio_base) ; // pci base 1
scriptDelayCycles(50) ; // Wait for bus controller to stabilize.
// MMIO base has changed, so use new base value plus offset from now on:
scriptWriteSingle(mmio_base + base18, xio_base) ; // pci base 2
scriptWriteSingle(mmio_base + subsystem_ids, this.board_id); // Sub-system and vendor ID - Enables PCI
// Set the upper 8-bits of the 16-bit XIO data to be primary function instead of default GPIO
// to enable Flash access:
scriptWriteSingle(mmio_base + GPIO_CTL1, mPRI_FunctionMode << 30 | // primary function mode for GPIO 31
mPRI_FunctionMode << 28 | // primary function mode for GPIO 30
mPRI_FunctionMode << 26 | // primary function mode for GPIO 29
mPRI_FunctionMode << 24 | // primary function mode for GPIO 28
mPRI_FunctionMode << 22 | // primary function mode for GPIO 27
mPRI_FunctionMode << 20 | // primary function mode for GPIO 26
mRetainCurrentMode << 18 | // retain current GPIO Mode for GPIO 25
mRetainCurrentMode << 16 | // retain current GPIO Mode for GPIO 24
mRetainCurrentMode << 14 | // retain current GPIO Mode for GPIO 23
mRetainCurrentMode << 12 | // retain current GPIO Mode for GPIO 22
mRetainCurrentMode << 10 | // retain current GPIO Mode for GPIO 21
mRetainCurrentMode << 8 | // retain current GPIO Mode for GPIO 20
mRetainCurrentMode << 6 | // retain current GPIO Mode for GPIO 19
mRetainCurrentMode << 4 | // retain current GPIO Mode for GPIO 18
mRetainCurrentMode << 2 | // retain current GPIO Mode for GPIO 17
mRetainCurrentMode << 0 ); // retain current GPIO Mode for GPIO 16
scriptWriteSingle(mmio_base + GPIO_CTL2, mRetainCurrentMode << 30 | // retain current GPIO Mode for GPIO 47
mRetainCurrentMode << 28 | // retain current GPIO Mode for GPIO 46
mRetainCurrentMode << 26 | // retain current GPIO Mode for GPIO 45
mRetainCurrentMode << 24 | // retain current GPIO Mode for GPIO 44
mRetainCurrentMode << 22 | // retain current GPIO Mode for GPIO 43
mRetainCurrentMode << 20 | // retain current GPIO Mode for GPIO 42
mRetainCurrentMode << 18 | // retain current GPIO Mode for GPIO 41
mRetainCurrentMode << 16 | // retain current GPIO Mode for GPIO 40
mRetainCurrentMode << 14 | // retain current GPIO Mode for GPIO 39
mRetainCurrentMode << 12 | // retain current GPIO Mode for GPIO 38
mRetainCurrentMode << 10 | // retain current GPIO Mode for GPIO 37
mPRI_FunctionMode << 8 | // primary function Mode for GPIO 36
mPRI_FunctionMode << 6 | // primary function Mode for GPIO 35
mPRI_FunctionMode << 4 | // primary function Mode for GPIO 34
mPRI_FunctionMode << 2 | // primary function Mode for GPIO 33
mPRI_FunctionMode << 0 ); // primary function Mode for GPIO 32
// stop tm32 core
scriptWriteSingle(mmio_base + TM32_CTL, mTM32_Stop); // TM32_CTL: stop
// DCS SDRAM mapping
scriptWriteSingle(mmio_base + APERTURE_WE, mDCS_DRAM_WE); // DCS_DRAM_WE: write enabled
scriptWriteSingle(mmio_base + DCS_DRAM_LO, sdram_base); // DCS_DRAM_LO
scriptWriteSingle(mmio_base + APERTURE_WE, mDCS_DRAM_WE); // DCS_DRAM_WE: write enabled
scriptWriteSingle(mmio_base + DCS_DRAM_HI, sdram_limit); // DCS_DRAM_HI
// TM SDRAM mapping
scriptWriteSingle(mmio_base + TM32_DRAM_LO, sdram_base); // TM32_DRAM_LO
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