register.h

NXP trimedira PNX1700的btscriptgen

#define ren_hi_shift                20      //NAND: REN high time.
#define ren_lo_shift                18      //NAND: REN low time.
#define dior_shift                  18      //IDE: DIOR and DIOW high time
#define we_lo_shift                 14      //NOR: WN time low
#define wen_hi_shift                16      //NAND: WEN high time
#define wen_lo_shift                14      //NAND: WEN low time
#define wait_shift                  9       //Delay between address and data phase if not using ACK.
#define offset_shift                5       //Starting address offset from start address of XIO aperture, in 8M increments.
#define type_68369                  0<<3    //68360 type device
#define type_NOR                    1<<3    //NOR Flash
#define type_NAND                   2<<3    //NAND Flash
#define type_IDE                    3<<3    //IDE
#define size8M                      0<<1    //8M
#define size16M                     1<<1    //16M
#define size32M                     2<<1    //32M
#define size64M                     3<<1    //64M
#define en_profile                  1<<0    //Enable sel profile

#define nand_ctrls              0x040830    //NAND-Flash profile controls
#define     nand_64M                1<<21   //1= 64-MB device support; 0 = 32 MB and smaller device
#define     nand_32M                0<<21   //1= 64-MB device support; 0 = 32 MB and smaller device
#define     includeData             1<<20   //1 = Include data in access cycle; 0 access does not include            
#define     Commands3               3<<18   //No. of commands to be used in NAND-Flash access
#define     Commands2               2<<18   //No. of commands to be used in NAND-Flash access
#define     Commands1               1<<18   //No. of commands to be used in NAND-Flash access
#define     Commands0               0<<18   //No. of commands to be used in NAND-Flash access
#define     Address3                3<<16   //No. of address phases to be used in NAND-Flash access.
#define     Address2                2<<16   //No. of address phases to be used in NAND-Flash access.
#define     Address1                1<<16   //No. of address phases to be used in NAND-Flash access.
#define     Address0                0<<16   //No. of address phases to be used in NAND-Flash access.
#define     command_b_shift         8       //This is the second command for NAND-Flash when two commands
#define     command_a_shift         0       //This is the first command for NAND-Flash



#define PLL0_CTL                0x047000    //PLL0 Control Register
#define PLL1_CTL                0x047004    //PLL1 Control Register
#define PLL2_CTL                0x047008    //PLL2 Control Register
#define PLL1_7_CTL              0x04700C    //PLL 1.728 GHz Control Register

#define CAB_DIV_PD              0x047034    //CAB Clocks divider powerdown signals
#define     mPd_192                 1<<8        //Power down 192 MHz divider in the CAB block.
#define     mPd_173                 1<<7        //Power down 173 MHz divider in the CAB block.
#define     mPd_157                 1<<6        //Power down 157 MHz divider in the CAB block.
#define     mPd_144                 1<<5        //Power down 144 MHz divider in the CAB block.
#define     mPd_133                 1<<4        //Power down 133 MHz divider in the CAB block.
#define     mPd_123                 1<<3        //Power down 123 MHz divider in the CAB block.
#define     mPd_115                 1<<2        //Power down 115 MHz divider in the CAB block.
#define     mPd_108                 1<<1        //Power down 108 MHz divider in the CAB block.
#define     mPd_102                 1<<0        //Power down 102 MHz divider in the CAB block.
#define     mPu_AllClks             0
                      
#define CLK_TM_CTL              0x047100    //TM3260 clock control
#define     mTurn_off_tm_ack        1<<5        //Indicates that the clock is being blocked.
#define     mTm_stretch_n           1<<4        //Deiables the 75/25 duty cycle adjust circuit.
#define     mSel_pwrdwn_clk_mmio    1<<3        //This bit allows the TM3260 to turn off the MMIO clock.
#define     mSel_clk_tm_27MHz_xtal  0<<1        //27 MHz xtal_clk.
#define     mSel_clk_tm_stretch_n   1<<1        //tm_stretch_n (output of the duty cycle stretcher).
#define     mSel_clk_tm_UNDEF       2<<1        //UNDEFINED
#define     mSel_clk_tm_AI_WS       3<<1        //AI_WS
#define     mEn_clk_tm              1<<0        //enable clk_tm

#define CLK_MEM_CTL             0x047104    //DDR Memory clock control
#define     mTurn_off_mem_ack       1<<3        //Indicates that the clock is being blocked.
#define     mSel_clk_mem_PLL2       1<<1        //PLL2.
#define     mSel_clk_mem_27MHz_xtal 2<<1        //27 MHz xtal_clk.
#define     mSel_clk_mem_GPIO7      3<<1        //GPIO[7].
#define     mEn_clk_mem             1<<0        //enable clk_mem

#define CLK_PCI_CTL             0x04710C    //PCI Clock control
#define     mTurn_off_pci_ack       1<<3        //Indicates that the clock is being blocked.
#define     mSel_clk_pci_27MHz      0<<1        //27 MHz xtal_clk
#define     mSel_clk_pci_33         1<<1        //clk_33
#define     mSel_clk_pci_xclk_16    2<<1        //xtal_clk/16 = 1.68 MHz
#define     mSel_clk_pci_AI_SD2     3<<1        //AI_SD[2]
#define     mEn_clk_pci             1<<0        //enable clk_pci

#define CLK_MMIO_CTL            0x04712C    //MMIO Clock control, a.k.a. DCS clock
#define     mTurn_off_mmio_ack      1<<6        //Indicates that the clock is being blocked.
#define     m102_clk_dtl_mmio_src   0<<3        //clk_102
#define     m108_clk_dtl_mmio_src   1<<3        //clk_108
#define     m115_clk_dtl_mmio_src   2<<3        //clk_115
#define     m123_clk_dtl_mmio_src   3<<3        //clk_123
#define     m133_clk_dtl_mmio_src   4<<3        //clk_133
#define     m144_clk_dtl_mmio_src   5<<3        //clk_144
#define     m157_clk_dtl_mmio_src   6<<3        //clk_157
#define     m54_clk_dtl_mmio_src    7<<3        //clk_54 
#define     mClk_dtl_mmio_27MHz     0<<1        //PLL2.
#define     mClk_dtl_mmio_src       1<<1        //27 MHz xtal_clk.
#define     mClk_dtl_mmio_27MHz2    2<<1        //GPIO[7].
#define     mClk_dtl_mmio_AO_SD3    3<<1        //enable clk_mem
#define     mEn_dtl_mmio            1<<0        //enable clk_dtl_mmio

#define RST_CTL                 0x060000    //RST_CTL is set on every time an hardware or software reset occurs.
#define     mDO_SW_RST              1<<2        //Do Software Reset. 
#define     mREL_SYS_RST_OUT        1<<1        //Release System Reset of External Peripherals.
#define     mASSERT_SYS_RST_OUT     1<<0        //Do System Reset of External Peripherals.

#define TM_DBG_N_DATA_OUT       0x061004    //Output register for data going to the JTAG

#define DCS_DRAM_LO             0x063200    //16-bit DCS-to-MTL memory range low register.
#define DCS_DRAM_HI             0x063204    //16-bit DCS-to-MTL memory range high register.

#define APERTURE_WE             0x063208    //Write enable register for DCS_DRAM_HI and DCS_DRAM_LO registers.
#define     mDCS_DRAM_WE            1<<0

#define IP_2031_CTL             0x065000    //DDR GENERAL CONTROL
#define     mHALT                   1<<15       //Halt when not in halt mode.
#define     mAUTO_HALT              1<<14       //Allow automatic halt.
#define     mWARM_START             1<<13       //Perform a warm start of the controller. 
#define     mDIS_WRITE_INT          1<<4        //DDR write burst cannot be interrupted by following read command.
#define     mDDR_DQS_PER_BYTE       1<<3        //A separate 揹qs