register.h

NXP trimedira PNX1700的btscriptgen

//-----------------------------------------------------------------------------
// FILE NAME:    register.h
//
// DESCRIPTION:  This header file describes registor addresses and
//               corresponding bit definitions.
//
// NOTES:
//

#ifndef PNX_REGISTER_H
#define PNX_REGISTER_H

/***************************
* Included Files           *
****************************/
//#include <register.h>

/***************************
* Macro definitions        *
****************************/
// Register locations
#define default_base            0x1BE00000  //PCI configuration Base address for MMIO.

#define pci_setup               0x040010    //PCI Setup register
#define     dis_reqgnt              1<<30       //Disable use of REQ/GNT when using internal arbiter.
#define     dis_reqgnt_a            1<<29       //Disable use of REQ_A/GNT_A when using internal arbiter.
#define     dis_reqgnt_b            1<<28       //Disable use of REQ_B/GNT_B when using internal arbiter.
#define     d2_support              1<<27       //Enable Support for D2 power state.
#define     d1_support              1<<26       //Enable Support for D1 power state
#define     en_ta                   1<<24       //Terminate restricted access attempt with target abort.
#define     en_pci2mmi              1<<23       //Enable memory hwy interface.
#define     en_xio                  1<<22       //Enable XIO functionality.
#define     base18_prefetchable     1<<21       //PCI base address 18 is a prefetchable memory aperture.
#define     base18_siz_16Mb         3<<18       //16Mb aperture size located by PCI cfg base18.
#define     base18_siz_32Mb         4<<18       //32Mb aperture size located by PCI cfg base18.
#define     base18_siz_64Mb         5<<18       //64Mb aperture size located by PCI cfg base18.
#define     base18_siz_128Mb        6<<18       //128Mb aperture size located by PCI cfg base18.
#define     en_base18               1<<17       //Enable 3rd aperture, PCI base address 18.
#define     base14_prefetchable     1<<16       //PCI Base address 14 is a non-prefetchable memory aperture.
#define     base14_siz              0<<12       //The size of aperture located by PCI cfg base 14 is 000 = 2 MB.
#define     en_base14               1<<11       //Enable 2nd aperture, PCI base address 14.
#define     base10_prefetchable     1<<10       //PCI Base address 10 is a prefetchable memory aperture.
#define     base10_siz16Mb          3<<7        //16Mb aperture size located by PCI cfg base 10.
#define     base10_siz32Mb          4<<7        //32Mb aperture size located by PCI cfg base 10.
#define     base10_siz64Mb          5<<7        //64Mb aperture size located by PCI cfg base 10.
#define     base10_siz128Mb         6<<7        //128Mb aperture size located by PCI cfg base 10.
#define     en_config_manag         1<<1        //Enable configuration management.
#define     en_pci_arb              1<<0        //Enable internal PCI system arbitration.



#define pci_control             0x040014    //PCI Control register
#define     dis_swapper2targ        1<<16       //Disable byte swapping in big endian mode from DCS to PCI path.
#define     dis_swapper2intreg      1<<15       //Disable byte swapping in big endian mode from PCI to PCI mmio registers.
#define     dis_swapper2dtlinit     1<<14       //Disable byte swapping in big endian mode from PCI to DCS.
#define     regs_wr_post_en         1<<13       //Enable write posting to internal PCI registers.
#define     xio_wr_post_en          1<<12       //Enable write posting to XIO address range.
#define     pci2_wr_post_en         1<<11       //Enable write posting to pci_base2 address range.
#define     pci1_wr_post_en         1<<10       //Enable write posting to pci_base1 address range.
#define     en_serr_seen            1<<9        //Enable monitoring of the SERR pin.                        
#define     en_base10_spec_rd       1<<6        //Read ahead to optimize PCI read latency to base 10.
#define     en_base14_spec_rd       1<<5        //Read ahead to optimize PCI read latency to base 14.
#define     en_base18_spec_rd       1<<4        //Read ahead to optimize PCI read latency to base 18.
#define     disable_subword2_10     1<<3        //Disable subword access to/from Base10 aperture.
#define     disable_subword2_14     1<<2        //Disable subword access to/from Base14 aperture.
#define     disable_subword2_18     1<<1        //Disable subword access to/from Base18 aperture.
#define     en_retry_timer          1<<0        //Enables timer for 16 tic rule enforcer. This bit does not affect access to the XIO aperture.

#define config_cmd_stat         0x040044    //Image of configuration command and status register (config reg 04)
#define     mFastBtoB               1<<9
#define     mSERR                   1<<8
#define     mParityErr              1<<6
#define     mMemWrite               1<<4
#define     mBusMaster              1<<2
#define     mMemSpace               1<<1

#define base10                  0x040050    //Image of configuration base address10 (config reg 10)
#define base14                  0x040054    //Image of configuration base address14 (config reg 14)
#define base18                  0x040058    //Image of configuration base address18 (config reg 18)

#define subsystem_ids           0x04006C    //Subsystem id, subsystem vendor id (config reg 2C)

#define dma_eaddr               0x040800    //PCI address for DMA transaction
#define dma_iaddr               0x040804    //Internal address for DMA transaction
#define dma_length              0x040808    //DMA length in words

#define dma_ctrl                0x04080C    //DMA control
#define     mSingle_data_phase      1<<10       //Limit DMA to single data phase transactions.
#define     mSnd2xio                1<<9        //1 = DMA will target XIO, 0 = DMA will target PCI.
#define     mFix_addr               1<<8        //1 = DMA will use fixed address, 0 = linear address.
#define     mMax_burst_size_8       0<<5        //8 data phase size PCI transaction.
#define     mMax_burst_size_16      1<<5        //16 data phase size PCI transaction.
#define     mMax_burst_size_32      2<<5        //32 data phase size PCI transaction.
#define     mMax_burst_size_64      3<<5        //64 data phase size PCI transaction.
#define     mMax_burst_size_128     4<<5        //128 data phase size PCI transaction.
#define     mMax_burst_size_256     5<<5        //256 data phase size PCI transaction.
#define     mMax_burst_size_512     6<<5        //512 data phase size PCI transaction.
#define     mMax_burst_size_Unl     7<<5        //No restriction in transfer length.
#define     mInit_dma               1<<4        //Initiate DMA transaction.
#define     mCmd_StartDMA           6<<0        //Start Command to be used for DMA. 

#define xio_sel0_prof           0x040814    //XIO sel0 profile
#define xio_sel1_prof           0x040818    //XIO sel1 profile
#define xio_sel2_prof           0x04081C    //XIO sel2 profile
#define xio_sel3_prof           0x040834    //XIO sel3 profile
#define xio_sel4_prof           0x040838    //XIO sel4 profile
#define misc_ctrl                   1<<24   //1 synchronous DSACK; 0 asynchronous DSACK.
#define en_16bit_xio                1<<23   //16 bit XIO device.
#define en_8bit_xio                 0<<23   //8 bit XIO device.
#define use_ack                     1<<22   //Wait for ACK.
#define ds_hi_shift                 18      //68360: DS time high.
#define we_hi_shift                 18      //NOR: WN time high.