hdb3prc.vhd

HDB3编解码

--********************************************************************************--
--                                                                                --
--  HDB3 Processor                                                                --
--                                                                                --
--********************************************************************************--



library IEEE;
use IEEE.std_logic_1164.all;


entity hdb3prc is
	port
	(
		hdb3x : in std_logic ;  --hdb3 input
        	hdb3y : in std_logic ;	--hdb3 input	  
        	hdbx : out std_logic ;	--hdb3 output	
		hdby : out std_logic ;	--hdb3 output	
		Tclk_hdb3 : out std_logic;	
        	data : in std_logic ;	--NRZ input		
		nrz : out std_logic ;	--NRZ output
		clk : in std_logic ;
        	clk2m : out std_logic;
		clk2mlocal: in std_logic;
--		ctrl: in std_logic; 
                clkmod: in  std_logic;
		aisalm: out std_logic;
		losalm: out std_logic;
		reset : in std_logic 
	
	);
begin
end hdb3prc;


architecture structure of hdb3prc is
	signal clk2mtmp: std_logic;
	signal lostmp: std_logic;
	signal Tclk_hdb3_tmp,Tclk_hdb3_dly0,Tclk_hdb3_dly1,Tclk_hdb3_dly2,Tclk_hdb3_dly3: std_logic;
	component hdb3dec
	port
		(
		hdb3x : in std_logic ;
        	hdb3y : in std_logic ;
		clk : in std_logic ;
		reset : in std_logic ;
		nrz : out std_logic ;
        	clk2m :out std_logic;
		clk2mlocal: in std_logic;
		aisalm: out std_logic;
		losalm: out std_logic 
		) ;
	end component ;

	component hdb3enc
	port
        	(
        	clk2m  : in std_logic ;
		clk2mlocal: in std_logic;
--		ctrl:  in std_logic;
                clkmod : in std_logic;
        	data : in std_logic ;
		reset: in std_logic ;
        	hdbx : out std_logic ;
		hdby : out std_logic;
		Tclk_hdb3 : out std_logic;
		los: in std_logic 
    		) ;
	end component ;
            
begin
		
	u1: hdb3dec
	        port map (hdb3x=>hdb3x, hdb3y=>hdb3y, clk=>clk, reset=>reset, nrz=>nrz, clk2m=>clk2mtmp , clk2mlocal=>clk2mlocal, aisalm => aisalm, losalm => lostmp) ;

	u2: hdb3enc
        	port map (clk2m=>clk2mtmp, clk2mlocal=>clk2mlocal, clkmod=>clkmod,data=>data, reset=>reset, hdbx=>hdbx, hdby=>hdby, Tclk_hdb3=>Tclk_hdb3_tmp,los=>lostmp) ;

	clk2m <= clk2mtmp;	
	losalm <= lostmp;
	
	process(clk)
	begin
	    if rising_edge(clk) then
		Tclk_hdb3_dly0 <= Tclk_hdb3_tmp;
		Tclk_hdb3_dly1 <= Tclk_hdb3_dly0;
		Tclk_hdb3_dly2 <= Tclk_hdb3_dly1;
		Tclk_hdb3_dly3 <= Tclk_hdb3_dly2;
	    end if;
	end process;
	
	Tclk_hdb3 <= Tclk_hdb3_dly2;

end structure ;