cnt4.vhd

HDB3编解码

--********************************************************************************--
--                                                                                --
--  Loadable 4-bit counter                                                        --
--                                                                                --
--********************************************************************************--



library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;


entity cnt4 is
	port
		(
		clk,load:in std_logic;
		reset:in std_logic;
		p:in std_logic_vector(3 downto 0);
		q:out std_logic_vector(3 downto 0)
		);
end cnt4;

architecture behavior of cnt4 is
	signal result:std_logic_vector(3 downto 0);
begin
   	q<=result;
   	process(reset,clk)
   	begin	
		if (reset='0') then
			result<="0000";
		elsif (clk'event) and (clk='1') then
      			if (load='1') then
				result<=p;
			else
				result<=result+1;
			end if;
		end if;
  	end process;
end behavior;  


architecture structure of cnt4 is
	signal add,d,result:std_logic_vector(3 downto 0);
	signal temp:std_logic_vector(1 downto 0);
begin
	q<=result;

	add(0)<=not(result(0));
	add(1)<=result(0) xor result(1);
	temp(0)<=result(0) and result(1);
	add(2)<=temp(0) xor result(2);
	temp(1)<=temp(0) and result(2);
	add(3)<=temp(1) xor result(3);
	
	d(0)<=(load and p(0)) or ((not load) and add(0));
	d(1)<=(load and p(1)) or ((not load) and add(1));
	d(2)<=(load and p(2)) or ((not load) and add(2));
	d(3)<=(load and p(3)) or ((not load) and add(3));
		
	process(reset, clk)
	begin
		if (reset='0') then
			result<="0000";
		elsif (clk'event)and(clk='1') then
			result<=d;
		end if;
	end process;
end structure;

configuration conf of cnt4 is
	for behavior
	end for;
end conf;