decoder.vhd

来自「HDB3编解码」· VHDL 代码 · 共 65 行

--********************************************************************************--
--                                                                                --
--  HDB3 code decoder                                                             --
--                                                                                --
--********************************************************************************--



library IEEE ;
use IEEE.std_logic_1164.all;


entity decoder is
	port
	(
		sgnl : in std_logic_vector (1 downto 0) ;
		clk2m : in std_logic ;
		reset : in std_logic ;
		data : out std_logic 
	);
begin
end decoder ;


architecture structure of decoder is 
	signal code : std_logic ;
	signal chs : std_logic ;
	signal zero4 : std_logic ;
	signal d : std_logic_vector (3 downto 0) ;
begin
	process(reset, clk2m)
	begin
		if (reset='0') then
			d<="0000";
			data<='0';
		elsif (clk2m'event) and (clk2m='1') then
			d(0)<=code ;
			d(1)<=d(0) and (not zero4);
			d(2)<=d(1) ;
			d(3)<=d(2) ;
			data<=d(3) and (not zero4) ;
		end if ;
	end process;

	process(reset, clk2m)
	begin
		if (reset='0') then
			chs<='0';
		elsif (clk2m'event) and (clk2m='1') then
			chs<=(sgnl(0)and(not sgnl(1)))or((not (sgnl(0) xor sgnl(1))) and chs) ;
	        end if ;
	end process ;

	process(reset, clk2m)
	begin
		if (reset='0') then
			zero4<='0';
		elsif (clk2m'event) and (clk2m='1') then
			zero4<=(chs and sgnl(0)) or ((not chs) and sgnl(1)) ;
		end if ;
	end process ;			

	code<=sgnl(0) xor sgnl(1) ;
end structure ;