2440init.s

很不错的基于UCOS2的GUI源码

;;; Copyright ARM Ltd 2001. All rights reserved.
;
; This module performs ROM/RAM remapping (if required), initializes stack 
; pointers and interrupts for each mode, and finally branches to __main in 
; the C library (which eventually calls main()).
;
; On reset, the ARM core starts up in Supervisor (SVC) mode, in ARM state, 
; with IRQ and FIQ disabled.

	GET  ..\2440_CODE\option.inc
	GET  ..\2440_CODE\memcfg.inc
	GET  ..\2440_CODE\2440addr.inc

BIT_SELFREFRESH EQU	(1<<22)



        AREA    Init, CODE, READONLY
        CODE32

USERMODE    EQU 	0x10
FIQMODE     EQU 	0x11
IRQMODE     EQU 	0x12
SVCMODE     EQU 	0x13
ABORTMODE   EQU 	0x17
UNDEFMODE   EQU 	0x1b

MODEMASK    EQU 	0x1f
NOINT       EQU 	0xc0

I_Bit       EQU     0x80 ; when I bit is set, IRQ is disabled
F_Bit       EQU     0x40 ; when F bit is set, FIQ is disabled



;The location of stacks ,Offsets must be 8 byte aligned.
UserStack	EQU	(_STACK_BASEADDRESS-0x3800)	;0x33ff4800 ~ 4k
SVCStack    EQU	(_STACK_BASEADDRESS-0x2800) ;0x33ff5800 ~

UndefStack	EQU	(_STACK_BASEADDRESS-0x2400) ;0x33ff5c00 ~
AbortStack	EQU	(_STACK_BASEADDRESS-0x2000) ;0x33ff6000 ~
IRQStack    EQU	(_STACK_BASEADDRESS-0x1000)	;0x33ff7000 ~
FIQStack	EQU	(_STACK_BASEADDRESS-0x0)	;0x33ff8000 ~ 


        EXPORT ResetHandler
		IMPORT __main
ResetHandler

        BL      InitCPU               
        BL      InitStack         

        B       __main         ; Jump to the entry point of C program 


InitCPU 
	
	ldr	r0,=WTCON       ;watch dog disable
	ldr	r1,=0x0
	str	r1,[r0]
			
	
	;禁止中断
	ldr	r0,=INTMSK
	ldr	r1,=0xffffffff  ;all interrupt disable
	str	r1,[r0]
	
	;禁止子中断
	ldr	r0,=INTSUBMSK
	ldr	r1,=0x7fff		;all sub interrupt disable
	str	r1,[r0]
	
	;时钟控制设置
	;To reduce PLL lock time, adjust the LOCKTIME register.
	ldr	r0,=LOCKTIME
	ldr	r1,=0xffffff
	str	r1,[r0]
	
	
  
	[ {FALSE}
		; rGPFDAT = (rGPFDAT & ~(0xf<<4)) | ((~data & 0xf)<<4);
		; Led_Display
		;set GPF[7:4] Output 
		ldr	r0,=GPFCON
		ldr	r1,=0x5500
		str	r1,[r0]
		;set GPF[7:5] = 0 GPF[4] = 1
		ldr	r0,=GPFDAT
		ldr	r1,=0x10
		str	r1,[r0]
	]

	;时钟控制设置
	;To reduce PLL lock time, adjust the LOCKTIME register.
	ldr	r0,=LOCKTIME
	ldr	r1,=0xffffff
	str	r1,[r0]
	
	IF 1 = 1
    [ PLL_ON_START
		; Added for confirm clock divide. for 2440.
		; Setting value Fclk:Hclk:Pclk
		ldr	r0,=CLKDIVN
		ldr	r1,=CLKDIV_VAL		; 0=1:1:1, 1=1:1:2, 2=1:2:2, 3=1:2:4, 4=1:4:4, 5=1:4:8, 6=1:3:3, 7=1:3:6.
		str	r1,[r0]
	
		;bl	Led_Test
		;mov	r0, #0x56000000
		;mov	r1, #0x5500
		;str	r1, [r0, #0x50]
	
		;program has not been copied, so use these directly, hzh
		[ CLKDIV_VAL>1 		; means Fclk:Hclk is not 1:1.
			mrc p15,0,r0,c1,c0,0
			orr r0,r0,#0xc0000000;R1_nF:OR:R1_iA
			mcr p15,0,r0,c1,c0,0
		|
			mrc p15,0,r0,c1,c0,0
			bic r0,r0,#0xc0000000;R1_iA:OR:R1_nF
			mcr p15,0,r0,c1,c0,0
		]
	
		;Configure UPLL
		ldr	r0, =UPLLCON
		ldr	r1, =((U_MDIV<<12)+(U_PDIV<<4)+U_SDIV)  
		str	r1, [r0]
		nop	; Caution: After UPLL setting, at least 7-clocks delay must be inserted for setting hardware be completed.
		nop
		nop
		nop
		nop
		nop
		nop
		;Configure MPLL
		ldr	r0, =MPLLCON
		ldr	r1, =((M_MDIV<<12)+(M_PDIV<<4)+M_SDIV)  ;Fin=12MHz
		str	r1, [r0]
    ]
    ENDIF
    
	;Set memory control registers
	;要注意存取SMRDATA的位置无关性
 	;ldr	r0,=SMRDATA
 	adrl	r0, SMRDATA	;be careful!, hzh
	ldr	r1,=BWSCON	;BWSCON Address
	add	r2, r0, #52	;End address of SMRDATA

0
	ldr	r3, [r0], #4
	str	r3, [r1], #4
	cmp	r2, r0
	bne	%B0
	
	
	;===delay, hzh
	;等待SDRAM自刷新有效
	mov	r0, #&1000
1
	subs	r0, r0, #1
	bne	%B1
	;===	

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;       When EINT0 is pressed,  Clear SDRAM 
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; check if EIN0 button is pressed
	;设置GPF[7:0]为输入且拉高
	ldr	r0,=GPFCON
	ldr	r1,=0x0
	str	r1,[r0]
	ldr	r0,=GPFUP
	ldr	r1,=0xff
	str	r1,[r0]
	;读取GPF[7:0]引脚值,GPF[0]为高时不清SDRAM
	ldr	r1,=GPFDAT
	ldr	r0,[r1]
	bic	r0,r0,#(0x1e<<1)  ; bit clear
	tst	r0,#0x1
	bne %F1

; Clear SDRAM Start
  	;设置GPF[7:4]输出，GPF[3:0]为EINT[3:0]
	ldr	r0,=GPFCON
	ldr	r1,=0x55aa
	str	r1,[r0]
	;设置输入口为拉高
;	ldr	r0,=GPFUP
;	ldr	r1,=0xff
;	str	r1,[r0]
	;输出口输出0 GPF[7:4]接LED
	ldr	r0,=GPFDAT
	ldr	r1,=0x0
	str	r1,[r0]	;LED=****

	;清楚SDRAM
	mov r1,#0
	mov r2,#0
	mov r3,#0
	mov r4,#0
	mov r5,#0
	mov r6,#0
	mov r7,#0
	mov r8,#0
	
	ldr	r9,=0x2000000   ;64MB
	ldr	r0,=0x30000000
0	
	stmia	r0!,{r1-r8}
	subs	r9,r9,#32 
	bne	%B0
	
1
    mov	pc,lr

	
	
    LTORG
SMRDATA DATA
; Memory configuration should be optimized for best performance
; The following parameter is not optimized.
; Memory access cycle parameter strategy
; 1) The memory settings is  safe parameters even at HCLK=75Mhz.
; 2) SDRAM refresh period is for HCLK<=75Mhz.

	DCD (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+(B7_BWSCON<<28))
	DCD ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC))   ;GCS0
	DCD ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC))   ;GCS1
	DCD ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC))   ;GCS2
	DCD ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC))   ;GCS3
	DCD ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC))   ;GCS4
	DCD ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC))   ;GCS5
	DCD ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))    ;GCS6
	DCD ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))    ;GCS7
	DCD ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Tsrc<<18)+(Tchr<<16)+REFCNT)

	DCD 0xb2	    ;SCLK power saving mode, BANKSIZE 128M/128M
	;DCD 0x32	    ;SCLK power saving mode, BANKSIZE 128M/128M
	;DCD 0x02	    ;SCLK power saving disable, BANKSIZE 128M/128M

	DCD 0x30	    ;MRSR6 CL=3clk
	DCD 0x30	    ;MRSR7 CL=3clk
	
	
	
    	ALIGN
    	
InitStack
	;Don nt use DRAM,such as stmfd,ldmfd......
	;SVCstack is initialized before
	;Under toolkit ver 2.5, 'msr cpsr,r1' can be used instead of 'msr cpsr_cxsf,r1'
	
	;禁止中断
	ldr	r0,=INTMSK
	ldr	r1,=0xffffffff  ;all interrupt disable
	str	r1,[r0]
	
	;禁止子中断
	ldr	r0,=INTSUBMSK
	ldr	r1,=0x7fff		;all sub interrupt disable
	str	r1,[r0]

	
	mrs	r0,cpsr
	bic	r0,r0,#MODEMASK
	orr	r1,r0,#UNDEFMODE|NOINT
	msr	cpsr_cxsf,r1		;UndefMode
	ldr	sp,=UndefStack		; UndefStack=0x33FF_5C00

	orr	r1,r0,#ABORTMODE|NOINT
	msr	cpsr_cxsf,r1		;AbortMode
	ldr	sp,=AbortStack		; AbortStack=0x33FF_6000

	orr	r1,r0,#IRQMODE|NOINT
	msr	cpsr_cxsf,r1		;IRQMode
	ldr	sp,=IRQStack		; IRQStack=0x33FF_7000

	orr	r1,r0,#FIQMODE|NOINT
	msr	cpsr_cxsf,r1		;FIQMode
	ldr	sp,=FIQStack		; FIQStack=0x33FF_8000

	bic	r0,r0,#MODEMASK|NOINT
	orr	r1,r0,#SVCMODE
	msr	cpsr_cxsf,r1		;SVCMode
	ldr	sp,=SVCStack		; SVCStack=0x33FF_5800
	
	;USER mode has not be initialized.
    ;装irq中断处理程序.	
	IMPORT HandleIRQ
	IMPORT IRQ_ISR          
	
  	; Setup IRQ handler
	ldr	r0,=HandleIRQ         
    ldr	r1,=IRQ_ISR
	str	r1,[r0]

	mov	pc,lr
	;The LR register won nt be valid if the current mode is not SVC mode.    	
	
	

	
	IMPORT bottom_of_heap
	IMPORT top_of_stacks
	
	EXPORT __user_initial_stackheap
__user_initial_stackheap    
    LDR   r0,=bottom_of_heap
    LDR   r1,=top_of_stacks
    MOV   pc,lr
	
	  END