system.ptf.4.01

nios下的lcd驱动开发源代码（仅供参考）

            {
               format = "Logic";
               name = "M_src2";
               radix = "hexadecimal";
            }
            SIGNAL acj
            {
               format = "Logic";
               name = "A_ctrl_shift_rot";
               radix = "hexadecimal";
            }
            SIGNAL ack
            {
               format = "Logic";
               name = "A_ctrl_shift_logical ";
               radix = "hexadecimal";
            }
            SIGNAL acl
            {
               format = "Logic";
               name = "A_ctrl_rot_right";
               radix = "hexadecimal";
            }
            SIGNAL acm
            {
               format = "Logic";
               name = "A_ctrl_shift_rot_right";
               radix = "hexadecimal";
            }
            SIGNAL acn
            {
               format = "Logic";
               name = "A_shift_rot_done_nxt";
               radix = "hexadecimal";
            }
            SIGNAL aco
            {
               format = "Logic";
               name = "A_shift_rot_stall";
               radix = "hexadecimal";
            }
            SIGNAL acp
            {
               format = "Logic";
               name = "A_shift_rot_fill_bit";
               radix = "hexadecimal";
            }
            SIGNAL acq
            {
               format = "Logic";
               name = "A_shift_rot_cnt_nxt";
               radix = "hexadecimal";
            }
            SIGNAL acr
            {
               format = "Logic";
               name = "A_shift_rot_cnt";
               radix = "hexadecimal";
            }
            SIGNAL acs
            {
               format = "Logic";
               name = "A_shift_rot_result_nxt";
               radix = "hexadecimal";
            }
            SIGNAL act
            {
               format = "Logic";
               name = "A_shift_rot_result";
               radix = "hexadecimal";
            }
            SIGNAL acu
            {
               format = "Divider";
               name = "breaks";
               radix = "";
            }
            SIGNAL acv
            {
               format = "Logic";
               name = "hbreak_req";
               radix = "hexadecimal";
            }
            SIGNAL acw
            {
               format = "Logic";
               name = "oci_hbreak_req";
               radix = "hexadecimal";
            }
            SIGNAL acx
            {
               format = "Logic";
               name = "hbreak_enabled";
               radix = "hexadecimal";
            }
            SIGNAL acy
            {
               format = "Logic";
               name = "wait_for_one_post_bret_inst";
               radix = "hexadecimal";
            }
            SIGNAL acz
            {
               format = "Logic";
               name = "D_hbreak_refetch";
               radix = "hexadecimal";
            }
            SIGNAL ada
            {
               format = "Logic";
               name = "E_hbreak_refetch";
               radix = "hexadecimal";
            }
         }
      }
      MASTER custom_instruction_master
      {
         PORT_WIRING 
         {
         }
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "nios_custom_instruction";
            Data_Width = "32";
            Address_Width = "8";
            Max_Address_Width = "8";
            Base_Address = "N/A";
            Is_Visible = "0";
            Is_Custom_Instruction = "0";
            Is_Enabled = "0";
         }
      }
      MASTER data_master2
      {
         PORT_WIRING 
         {
            # The number and kind of ports that appear on this module
            # depends on the user's wizard-choices.
            # This section will be filled-in by the Generator_Program after
            # the module logic has been created and the ports are known.
         }
         SYSTEM_BUILDER_INFO 
         {
            Register_Incoming_Signals = "1";
            Bus_Type = "avalon";
            Data_Width = "32";
            Max_Address_Width = "31";
            Address_Width = "8";
            Is_Data_Master = "1";
            Has_IRQ = "0";
            Is_Enabled = "0";
         }
      }
      MASTER tightly_coupled_data_master_0
      {
         PORT_WIRING 
         {
            # The number and kind of ports that appear on this module
            # depends on the user's wizard-choices.
            # This section will be filled-in by the Generator_Program after
            # the module logic has been created and the ports are known.
         }
         SYSTEM_BUILDER_INFO 
         {
            Register_Incoming_Signals = "0";
            Bus_Type = "avalon";
            Data_Width = "32";
            Max_Address_Width = "31";
            Address_Width = "8";
            Is_Data_Master = "1";
            Has_IRQ = "0";
            Is_Enabled = "0";
            Connection_Limit = "1";
            Is_Channel = "1";
         }
      }
      MASTER tightly_coupled_data_master_1
      {
         PORT_WIRING 
         {
            # The number and kind of ports that appear on this module
            # depends on the user's wizard-choices.
            # This section will be filled-in by the Generator_Program after
            # the module logic has been created and the ports are known.
         }
         SYSTEM_BUILDER_INFO 
         {
            Register_Incoming_Signals = "0";
            Bus_Type = "avalon";
            Data_Width = "32";
            Max_Address_Width = "31";
            Address_Width = "8";
            Is_Data_Master = "1";
            Has_IRQ = "0";
            Is_Enabled = "0";
            Connection_Limit = "1";
            Is_Channel = "1";
         }
      }
      MASTER tightly_coupled_data_master_2
      {
         PORT_WIRING 
         {
            # The number and kind of ports that appear on this module
            # depends on the user's wizard-choices.
            # This section will be filled-in by the Generator_Program after
            # the module logic has been created and the ports are known.
         }
         SYSTEM_BUILDER_INFO 
         {
            Register_Incoming_Signals = "0";
            Bus_Type = "avalon";
            Data_Width = "32";
            Max_Address_Width = "31";
            Address_Width = "8";
            Is_Data_Master = "1";
            Has_IRQ = "0";
            Is_Enabled = "0";
            Connection_Limit = "1";
            Is_Channel = "1";
         }
      }
      MASTER tightly_coupled_data_master_3
      {
         PORT_WIRING 
         {
            # The number and kind of ports that appear on this module
            # depends on the user's wizard-choices.
            # This section will be filled-in by the Generator_Program after
            # the module logic has been created and the ports are known.
         }
         SYSTEM_BUILDER_INFO 
         {
            Register_Incoming_Signals = "0";
            Bus_Type = "avalon";
            Data_Width = "32";
            Max_Address_Width = "31";
            Address_Width = "8";
            Is_Data_Master = "1";
            Has_IRQ = "0";
            Is_Enabled = "0";
            Connection_Limit = "1";
            Is_Channel = "1";
         }
      }
      MASTER tightly_coupled_instruction_master_0
      {
         PORT_WIRING 
         {
            # The number and kind of ports that appear on this module
            # depends on the user's wizard-choices.
            # This section will be filled-in by the Generator_Program after
            # the module logic has been created and the ports are known.
         }
         SYSTEM_BUILDER_INFO 
         {
            Register_Incoming_Signals = "0";
            Bus_Type = "avalon";
            Data_Width = "32";
            Max_Address_Width = "31";
            Address_Width = "8";
            Is_Instruction_Master = "1";
            Has_IRQ = "0";
            Is_Enabled = "0";
            Connection_Limit = "1";
            Is_Channel = "1";
         }
      }
   }
   MODULE sys_clk_timer
   {
      class = "altera_avalon_timer";
      class_version = "2.1";
      iss_model_name = "altera_avalon_timer";
      SLAVE s1
      {
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Is_Printable_Device = "0";
            Address_Alignment = "native";
            Address_Width = "3";
            Data_Width = "16";
            Has_IRQ = "1";
            Read_Wait_States = "1";
            Write_Wait_States = "0";
            Base_Address = "0x00100800";
            MASTERED_BY cpu_0/data_master
            {
               priority = "1";
            }
            IRQ_MASTER cpu_0/data_master
            {
               IRQ_Number = "0";
            }
         }
         PORT_WIRING 
         {
            PORT address
            {
               direction = "input";
               type = "address";
               width = "3";
            }
            PORT chipselect
            {
               direction = "input";
               type = "chipselect";
               width = "1";
            }
            PORT clk
            {
               direction = "input";
               type = "clk";
               width = "1";
            }
            PORT irq
            {
               direction = "output";
               type = "irq";
               width = "1";
            }
            PORT readdata
            {
               direction = "output";
               type = "readdata";
               width = "16";
            }
            PORT reset_n
            {
               direction = "input";
               type = "reset_n";
               width = "1";
            }
            PORT write_n
            {
               direction = "input";
               type = "write_n";
               width = "1";
            }
            PORT writedata
            {
               direction = "input";
               type = "writedata";
               width = "16";
            }
         }
      }
      SYSTEM_BUILDER_INFO 
      {
         Instantiate_In_System_Module = "1";
         Is_Enabled = "1";
         View 
         {
            Settings_Summary = "Timer with 1 ms timeout period.";
            MESSAGES 
            {
            }
            Is_Collapsed = "1";
         }
         Clock_Source = "clk";
      }
      WIZARD_SCRIPT_ARGUMENTS 
      {
         always_run = "1";
         fixed_period = "1";
         snapshot = "0";
         period = "1";
         period_units = "ms";
         reset_output = "0";
         timeout_pulse_output = "0";
         mult = "0.001";
      }
      HDL_INFO 
      {
         Simulation_HDL_Files = "";
         Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/sys_clk_timer.v";
         Precompiled_Simulation_Library_Files = "";
         Synthesis_Only_Files = "";
      }
      PORT_WIRING 
      {
      }
   }
   MODULE high_res_timer
   {
      class = "altera_avalon_timer";
      class_version = "2.1";
      iss_model_name = "altera_avalon_timer";
      SLAVE s1
      {
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Is_Printable_Device = "0";
            Address_Alignment = "native";
            Address_Width = "3";
            Data_Width = "16";
            Has_IRQ = "1";
            Read_Wait_States = "1";
            Write_Wait_States = "0";
            Base_Address = "0x00010820";
            MASTERED_BY cpu_0/data_master
            {
               priority = "1";
            }
            IRQ_MASTER cpu_0/data_master
            {
               IRQ_Number = "1";
            }
         }
         PORT_WIRING 
         {
            PORT address
            {
               direction = "input";
               type = "address";
               width = "3";
            }
            PORT chipselect
            {
               direction = "input";
               type = "chipselect";
               width = "1";
            }
            PORT clk
            {
               direction = "input";
               type = "clk";
               width = "1";
            }
            PORT irq
            {
               direction = "output";
               type = "irq";
               width = "1";
            }
            PORT readdata
            {
               direction = "output";
               type = "readdata";
               width = "16";
            }
            PORT reset_n
            {
               direction = "input";
               type = "reset_n";
               width = "1";
            }
            PORT write_n
            {
               direction = "input";
               type = "write_n";
               width = "1";
            }
            PORT writedata
            {
               direction = "input";
               type = "writedata";
               width = "16";
            }
         }
      }
      SYSTEM_BUILDER_INFO 
      {
         Instantiate_In_System_Module = "1";
         Is_Enabled = "1";
         View 
         {
            Settings_Summary = "Timer with 1 ms timeout period.";
            MESSAGES 
            {
            }
            Is_Collapsed = "1";
         }
         Clock_Source = "clk";
      }
      WIZARD_SCRIPT_ARGUMENTS 
      {