📄 system.ptf.4.01
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SYSTEM system
{
System_Wizard_Version = "4.01";
System_Wizard_Build = "214";
WIZARD_SCRIPT_ARGUMENTS
{
device_family = "CYCLONE";
clock_freq = "50000000";
generate_hdl = "1";
generate_sdk = "0";
do_build_sim = "0";
hdl_language = "verilog";
view_master_columns = "1";
view_master_priorities = "0";
board_class = "altera_nios_dev_board_cyclone_1c20";
name_column_width = "285";
desc_column_width = "285";
bustype_column_width = "0";
base_column_width = "75";
end_column_width = "75";
view_frame_window = "485:53:1002:464";
do_log_history = "0";
BOARD_INFO
{
CONFIGURATION epcs
{
length = "";
offset = "0x0";
reference_designator = "U59";
}
CONFIGURATION factory
{
length = "";
offset = "0x700000";
reference_designator = "U5";
}
CONFIGURATION user
{
length = "";
offset = "0x600000";
reference_designator = "U5";
}
JTAG_device_index = "1";
REFDES U5
{
base = "0x00800000";
}
REFDES U59
{
base = "0x00060000";
}
altera_avalon_cfi_flash
{
reference_designators = "U5";
}
altera_avalon_epcs_flash_controller
{
reference_designators = "U59";
}
class = "altera_nios_dev_board_cyclone_1c20";
class_version = "1.0";
device_family = "CYCLONE";
quartus_pgm_file = "system/altera_nios_dev_board_cyclone_1c20.sof";
quartus_project_file = "system/altera_nios_dev_board_cyclone_1c20.qpf";
reference_designators = "U59,U5";
sopc_system_file = "system/altera_nios_dev_board_cyclone_1c20.ptf";
}
CLOCKS
{
clk = "50000000";
}
device_family_id = "CYCLONE";
clock_column_width = "";
}
MODULE cpu_0
{
class = "altera_nios2";
class_version = "1.0";
iss_model_name = "altera_nios2";
HDL_INFO
{
PLI_Files = "";
Precompiled_Simulation_Library_Files = "";
Simulation_HDL_Files = "";
Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/cpu_0_test_bench.v, __PROJECT_DIRECTORY__/cpu_0_jtag_debug_module.v, __PROJECT_DIRECTORY__/cpu_0_jtag_debug_module_wrapper.v, __PROJECT_DIRECTORY__/cpu_0.v";
Synthesis_Only_Files = "";
}
MASTER instruction_master
{
PORT_WIRING
{
PORT i_address
{
direction = "output";
type = "address";
width = "22";
}
PORT i_read
{
direction = "output";
type = "read";
width = "1";
}
PORT i_readdata
{
direction = "input";
type = "readdata";
width = "32";
}
PORT i_readdatavalid
{
direction = "input";
type = "readdatavalid";
width = "1";
}
PORT i_waitrequest
{
direction = "input";
type = "waitrequest";
width = "1";
}
}
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Data_Width = "32";
Max_Address_Width = "31";
Address_Width = "8";
Is_Instruction_Master = "1";
Has_IRQ = "0";
Irq_Scheme = "individual_requests";
Interrupt_Range = "0-0";
Is_Enabled = "1";
}
}
MASTER data_master
{
PORT_WIRING
{
PORT d_address
{
direction = "output";
type = "address";
width = "22";
}
PORT d_byteenable
{
direction = "output";
type = "byteenable";
width = "4";
}
PORT d_irq
{
direction = "input";
type = "irq";
width = "32";
}
PORT d_read
{
direction = "output";
type = "read";
width = "1";
}
PORT d_readdata
{
direction = "input";
type = "readdata";
width = "32";
}
PORT d_waitrequest
{
direction = "input";
type = "waitrequest";
width = "1";
}
PORT d_write
{
direction = "output";
type = "write";
width = "1";
}
PORT d_writedata
{
direction = "output";
type = "writedata";
width = "32";
}
PORT jtag_debug_module_debugaccess_to_roms
{
direction = "output";
type = "debugaccess";
width = "1";
}
PORT clk
{
direction = "input";
type = "clk";
width = "1";
}
}
SYSTEM_BUILDER_INFO
{
Register_Incoming_Signals = "1";
Bus_Type = "avalon";
Data_Width = "32";
Max_Address_Width = "31";
Address_Width = "8";
Is_Data_Master = "1";
Has_IRQ = "1";
Irq_Scheme = "individual_requests";
Interrupt_Range = "0-31";
Is_Enabled = "1";
}
}
SLAVE jtag_debug_module
{
PORT_WIRING
{
PORT jtag_debug_module_address
{
direction = "input";
type = "address";
width = "9";
}
PORT jtag_debug_module_begintransfer
{
direction = "input";
type = "begintransfer";
width = "1";
}
PORT jtag_debug_module_byteenable
{
direction = "input";
type = "byteenable";
width = "4";
}
PORT jtag_debug_module_clk
{
direction = "input";
type = "clk";
width = "1";
}
PORT jtag_debug_module_debugaccess
{
direction = "input";
type = "debugaccess";
width = "1";
}
PORT jtag_debug_module_readdata
{
direction = "output";
type = "readdata";
width = "32";
}
PORT jtag_debug_module_reset
{
direction = "input";
type = "reset";
width = "1";
}
PORT jtag_debug_module_resetrequest
{
direction = "output";
type = "resetrequest";
width = "1";
}
PORT jtag_debug_module_select
{
direction = "input";
type = "chipselect";
width = "1";
}
PORT jtag_debug_module_write
{
direction = "input";
type = "write";
width = "1";
}
PORT jtag_debug_module_writedata
{
direction = "input";
type = "writedata";
width = "32";
}
PORT reset_n
{
direction = "input";
type = "reset_n";
width = "1";
}
}
SYSTEM_BUILDER_INFO
{
Read_Wait_States = "1";
Write_Wait_States = "1";
Register_Incoming_Signals = "1";
Bus_Type = "avalon";
Data_Width = "32";
Address_Width = "9";
Accepts_Internal_Connections = "1";
Requires_Internal_Connections = "instruction_master,data_master";
Accepts_External_Connections = "0";
Is_Enabled = "1";
Address_Alignment = "dynamic";
Base_Address = "0x00010000";
Is_Memory_Device = "1";
Is_Printable_Device = "0";
Uses_Tri_State_Data_Bus = "0";
Has_IRQ = "0";
JTAG_Hub_Base_Id = "593990";
JTAG_Hub_Instance_Id = "0";
MASTERED_BY cpu_0/instruction_master
{
priority = "1";
}
MASTERED_BY cpu_0/data_master
{
priority = "1";
}
IRQ_MASTER cpu_0/data_master
{
IRQ_Number = "NC";
}
}
}
WIZARD_SCRIPT_ARGUMENTS
{
asp_debug = "0";
asp_core_debug = "0";
CPU_Architecture = "nios2";
do_generate = "1";
cpu_selection = "f";
CPU_Implementation = "fast";
cache_has_dcache = "1";
cache_has_icache = "1";
cache_dcache_size = "2048";
cache_icache_size = "4096";
include_debug = "0";
include_trace = "0";
include_oci = "1";
debug_level = "2";
oci_offchip_trace = "0";
oci_onchip_trace = "0";
oci_data_trace = "0";
oci_trace_addr_width = "7";
oci_num_xbrk = "0";
oci_num_dbrk = "0";
oci_dbrk_trace = "0";
oci_dbrk_pairs = "0";
oci_num_pm = "0";
oci_pm_width = "40";
oci_debugreq_signals = "0";
oci_instance_number = "1";
hardware_multiply_present = "0";
hardware_divide_present = "0";
bht_ptr_sz = "8";
reset_slave = "offchip_memory_sram/s1";
reset_offset = "0x00000000";
exc_slave = "offchip_memory_sram/s1";
exc_offset = "0x00000020";
break_slave = "cpu_0/jtag_debug_module";
break_offset = "0x00000020";
break_slave_override = "";
break_offset_override = "0x20";
legacy_sdk_support = "0";
altera_internal_test = "0";
full_waveform_signals = "0";
activate_model_checker = "0";
activate_monitors_and_trace = "0";
bit_31_bypass_dcache = "1";
always_bypass_dcache = "0";
always_encrypt = "1";
hdl_sim_caches_cleared = "1";
allow_full_address_range = "0";
consistent_synthesis = "0";
ibuf_ptr_sz = "4";
jtb_ptr_sz = "5";
performance_counters_present = "0";
performance_counters_width = "32";
ras_ptr_sz = "4";
inst_decode_in_submodule = "0";
register_dependency_in_submodule = "0";
source_operands_in_submodule = "0";
alu_in_submodule = "0";
stdata_in_submodule = "0";
shift_rot_2N_in_submodule = "0";
control_regs_in_submodule = "0";
mult_cell_in_submodule = "0";
M_inst_result_mux_in_submodule = "0";
dcache_load_aligner_in_submodule = "0";
hardware_divide_in_submodule = "0";
mult_result_mux_in_submodule = "0";
shift_rotate_in_submodule = "0";
register_file_write_data_mux_in_submodule = "0";
avalon_imaster_in_submodule = "0";
avalon_dmaster_in_submodule = "0";
avalon_load_aligner_in_submodule = "0";
hbreak_test = "0";
iss_trace_on = "0";
iss_trace_warning = "1";
iss_trace_info = "1";
iss_trace_disassembly = "0";
iss_trace_registers = "0";
iss_trace_instr_count = "0";
iss_software_debug = "0";
iss_software_debug_port = "9996";
iss_memory_dump_start = "";
iss_memory_dump_end = "";
Boot_Copier = "boot_loader_cfi.srec";
Boot_Copier_EPCS = "boot_loader_epcs.srec";
CONSTANTS
{
CONSTANT __nios_catch_irqs__
{
value = "1";
comment = "Include panic handler for all irqs (needs uart)";
}
CONSTANT __nios_use_constructors__
{
value = "1";
comment = "Call c++ static constructors";
}
CONSTANT __nios_use_small_printf__
{
value = "1";
comment = "Smaller non-ANSI printf, with no floating point";
}
CONSTANT nasys_has_icache
{
value = "1";
comment = "True if instruction cache present";
}
CONSTANT nasys_icache_size
{
value = "4096";
comment = "Size in bytes of instruction cache";
}
CONSTANT nasys_icache_line_size
{
value = "32";
comment = "Size in bytes of each icache line";
}
CONSTANT nasys_icache_line_size_log2
{
value = "5";
comment = "Log2 size in bytes of each icache line";
}
CONSTANT nasys_has_dcache
{
value = "1";
comment = "True if instruction cache present";
}
CONSTANT nasys_dcache_size
{
value = "2048";
comment = "Size in bytes of data cache";
}
CONSTANT nasys_dcache_line_size
{
value = "4";
comment = "Size in bytes of each dcache line";
}
CONSTANT nasys_dcache_line_size_log2
{
value = "2";
comment = "Log2 size in bytes of each dcache line";
}
}
mainmem_slave = "offchip_memory_sram/s1";
datamem_slave = "offchip_memory_sram/s1";
maincomm_slave = "";
debugcomm_slave = "";
germs_monitor_id = "";
activate_trace = "1";
activate_monitors = "1";
activate_test_end_checker = "0";
clear_x_bits_ld_non_bypass = "1";
remove_hardware_multiplier = "0";
include_third_party_debug_port = "0";
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