📄 first_nios2_system.ptf
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}
PORT chipselect
{
direction = "input";
type = "chipselect";
width = "1";
}
PORT clk
{
direction = "input";
type = "clk";
width = "1";
}
PORT irq
{
direction = "output";
type = "irq";
width = "1";
}
PORT readdata
{
direction = "output";
type = "readdata";
width = "4";
}
PORT reset_n
{
direction = "input";
type = "reset_n";
width = "1";
}
PORT write_n
{
direction = "input";
type = "write_n";
width = "1";
}
PORT writedata
{
direction = "input";
type = "writedata";
width = "4";
}
}
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Has_IRQ = "1";
Address_Width = "2";
Data_Width = "4";
Base_Address = "0x00900820";
Address_Alignment = "native";
Read_Wait_States = "1";
Write_Wait_States = "0";
MASTERED_BY cpu/data_master
{
priority = "1";
}
IRQ_MASTER cpu/data_master
{
IRQ_Number = "2";
}
}
}
SYSTEM_BUILDER_INFO
{
Date_Modified = "";
Is_Enabled = "1";
Instantiate_In_System_Module = "1";
Wire_Test_Bench_Values = "1";
Clock_Source = "clk";
View
{
Settings_Summary = " 4-bit PIO using <br>
input pins with edge type ANY and interrupt source EDGE
";
MESSAGES
{
}
Is_Collapsed = "1";
}
}
WIZARD_SCRIPT_ARGUMENTS
{
Do_Test_Bench_Wiring = "0";
Driven_Sim_Value = "0x0000";
has_tri = "0";
has_out = "0";
has_in = "1";
capture = "1";
edge_type = "ANY";
irq_type = "EDGE";
}
}
MODULE reconfig_request_pio
{
class = "altera_avalon_pio";
class_version = "2.2";
HDL_INFO
{
Precompiled_Simulation_Library_Files = "";
Simulation_HDL_Files = "";
Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/reconfig_request_pio.v";
Synthesis_Only_Files = "";
}
PORT_WIRING
{
PORT bidir_port
{
direction = "inout";
width = "1";
}
}
SLAVE s1
{
PORT_WIRING
{
PORT address
{
direction = "input";
type = "address";
width = "2";
}
PORT chipselect
{
direction = "input";
type = "chipselect";
width = "1";
}
PORT clk
{
direction = "input";
type = "clk";
width = "1";
}
PORT readdata
{
direction = "output";
type = "readdata";
width = "1";
}
PORT reset_n
{
direction = "input";
type = "reset_n";
width = "1";
}
PORT write_n
{
direction = "input";
type = "write_n";
width = "1";
}
PORT writedata
{
direction = "input";
type = "writedata";
width = "1";
}
}
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Has_IRQ = "0";
Address_Width = "2";
Data_Width = "1";
Base_Address = "0x00900830";
Address_Alignment = "native";
Read_Wait_States = "1";
Write_Wait_States = "0";
MASTERED_BY cpu/data_master
{
priority = "1";
}
IRQ_MASTER cpu/data_master
{
IRQ_Number = "NC";
}
}
}
SYSTEM_BUILDER_INFO
{
Date_Modified = "";
Is_Enabled = "1";
Instantiate_In_System_Module = "1";
Wire_Test_Bench_Values = "1";
Clock_Source = "clk";
View
{
Settings_Summary = " 1-bit PIO using <br>
tri-state pins with edge type NONE and interrupt source NONE
";
MESSAGES
{
}
Is_Collapsed = "1";
}
}
WIZARD_SCRIPT_ARGUMENTS
{
Do_Test_Bench_Wiring = "0";
Driven_Sim_Value = "0x0000";
has_tri = "1";
has_out = "0";
has_in = "0";
capture = "0";
edge_type = "NONE";
irq_type = "NONE";
}
}
MODULE lcd_pio
{
class = "altera_avalon_pio";
class_version = "2.2";
HDL_INFO
{
Precompiled_Simulation_Library_Files = "";
Simulation_HDL_Files = "";
Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/lcd_pio.v";
Synthesis_Only_Files = "";
}
PORT_WIRING
{
PORT bidir_port
{
direction = "inout";
width = "11";
}
}
SLAVE s1
{
PORT_WIRING
{
PORT address
{
direction = "input";
type = "address";
width = "2";
}
PORT chipselect
{
direction = "input";
type = "chipselect";
width = "1";
}
PORT clk
{
direction = "input";
type = "clk";
width = "1";
}
PORT readdata
{
direction = "output";
type = "readdata";
width = "11";
}
PORT reset_n
{
direction = "input";
type = "reset_n";
width = "1";
}
PORT write_n
{
direction = "input";
type = "write_n";
width = "1";
}
PORT writedata
{
direction = "input";
type = "writedata";
width = "11";
}
}
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Has_IRQ = "0";
Address_Width = "2";
Data_Width = "11";
Base_Address = "0x00900840";
Address_Alignment = "native";
Read_Wait_States = "1";
Write_Wait_States = "0";
MASTERED_BY cpu/data_master
{
priority = "1";
}
IRQ_MASTER cpu/data_master
{
IRQ_Number = "NC";
}
}
}
SYSTEM_BUILDER_INFO
{
Date_Modified = "";
Is_Enabled = "1";
Instantiate_In_System_Module = "1";
Wire_Test_Bench_Values = "1";
Clock_Source = "clk";
View
{
Settings_Summary = " 11-bit PIO using <br>
tri-state pins with edge type NONE and interrupt source NONE
";
MESSAGES
{
}
Is_Collapsed = "1";
}
}
WIZARD_SCRIPT_ARGUMENTS
{
Do_Test_Bench_Wiring = "0";
Driven_Sim_Value = "0x0000";
has_tri = "1";
has_out = "0";
has_in = "0";
capture = "0";
edge_type = "NONE";
irq_type = "NONE";
}
}
MODULE led_pio
{
class = "altera_avalon_pio";
class_version = "2.2";
HDL_INFO
{
Precompiled_Simulation_Library_Files = "";
Simulation_HDL_Files = "";
Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/led_pio.v";
Synthesis_Only_Files = "";
}
PORT_WIRING
{
PORT out_port
{
direction = "output";
width = "8";
}
}
SLAVE s1
{
PORT_WIRING
{
PORT address
{
direction = "input";
type = "address";
width = "2";
}
PORT chipselect
{
direction = "input";
type = "chipselect";
width = "1";
}
PORT clk
{
direction = "input";
type = "clk";
width = "1";
}
PORT reset_n
{
direction = "input";
type = "reset_n";
width = "1";
}
PORT write_n
{
direction = "input";
type = "write_n";
width = "1";
}
PORT writedata
{
direction = "input";
type = "writedata";
width = "8";
}
}
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Has_IRQ = "0";
Address_Width = "2";
Data_Width = "8";
Base_Address = "0x00900850";
Address_Alignment = "native";
Read_Wait_States = "1";
Write_Wait_States = "0";
MASTERED_BY cpu/data_master
{
priority = "1";
}
IRQ_MASTER cpu/data_master
{
IRQ_Number = "NC";
}
}
}
SYSTEM_BUILDER_INFO
{
Date_Modified = "";
Is_Enabled = "1";
Instantiate_In_System_Module = "1";
Wire_Test_Bench_Values = "1";
Clock_Source = "clk";
View
{
Settings_Summary = " 8-bit PIO using <br>
output pins";
MESSAGES
{
}
Is_Collapsed = "1";
}
}
WIZARD_SCRIPT_ARGUMENTS
{
Do_Test_Bench_Wiring = "0";
Driven_Sim_Value = "0x0000";
has_tri = "0";
has_out = "1";
has_in = "0";
capture = "0";
edge_type = "NONE";
irq_type = "NONE";
}
}
MODULE seven_seg_pio
{
class = "altera_avalon_pio";
class_version = "2.2";
HDL_INFO
{
Precompiled_Simulation_Library_Files = "";
Simulation_HDL_Files = "";
Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/seven_seg_pio.v";
Synthesis_Only_Files = "";
}
PORT_WIRING
{
PORT out_port
{
direction = "output";
width = "16";
}
}
SLAVE s1
{
PORT_WIRING
{
PORT address
{
direction = "input";
type = "address";
width = "2";
}
PORT chipselect
{
direction = "input";
type = "chipselect";
width = "1";
}
PORT clk
{
direction = "input";
type = "clk";
width = "1";
}
PORT reset_n
{
direction = "input";
type = "reset_n";
width = "1";
}
PORT write_n
{
direction = "input";
type = "write_n";
width = "1";
}
PORT writedata
{
direction = "input";
type = "writedata";
width = "16";
}
}
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Has_IRQ = "0";
Address_Width = "2";
Data_Width = "16";
Base_Address = "0x00900860";
Address_Alignment = "native";
Read_Wait_States = "1";
Write_Wait_States = "0";
MASTERED_BY cpu/data_master
{
priority = "1";
}
IRQ_MASTER cpu/data_master
{
IRQ_Number = "NC";
}
}
}
SYSTEM_BUILDER_INFO
{
Date_Modified = "";
Is_Enabled = "1";
Instantiate_In_System_Module = "1";
Wire_Test_Bench_Values = "1";
Clock_Source = "clk";
View
{
Settings_Summary = " 16-bit PIO using <br>
output pins";
MESSAGES
{
}
Is_Collapsed = "0";
}
}
WIZARD_SCRIPT_ARGUMENTS
{
Do_Test_Bench_Wiring = "0";
Driven_Sim_Value = "0x0000";
has_tri = "0";
has_out = "1";
has_in = "0";
capture = "0";
edge_type = "NONE";
irq_type = "NONE";
}
}
}
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