📄 first_nios2_system.ptf
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read_char_stream = "";
showascii = "1";
read_le = "0";
write_le = "0";
}
SIMULATION
{
Fix_Me_Up = "";
DISPLAY
{
SIGNAL av_chipselect
{
name = "av_chipselect";
}
SIGNAL av_address
{
name = "av_address";
radix = "hexadecimal";
}
SIGNAL av_read_n
{
name = "av_read_n";
}
SIGNAL av_readdata
{
name = "av_readdata";
radix = "hexadecimal";
}
SIGNAL av_write_n
{
name = "av_write_n";
}
SIGNAL av_writedata
{
name = "av_writedata";
radix = "hexadecimal";
}
SIGNAL av_waitrequest
{
name = "av_waitrequest";
}
SIGNAL av_irq
{
name = "av_irq";
}
SIGNAL dataavailable
{
name = "dataavailable";
}
SIGNAL readyfordata
{
name = "readyfordata";
}
}
INTERACTIVE_IN drive
{
enable = "0";
file = "_input_data_stream.dat";
mutex = "_input_data_mutex.dat";
log = "_in.log";
rate = "100";
signals = "temp,list";
exe = "nios2-terminal";
}
INTERACTIVE_OUT log
{
enable = "1";
exe = "perl -- atail-f.pl";
file = "_output_stream.dat";
radix = "ascii";
signals = "temp,list";
}
}
HDL_INFO
{
Precompiled_Simulation_Library_Files = "";
Simulation_HDL_Files = "";
Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/jtag_uart.v";
Synthesis_Only_Files = "";
}
PORT_WIRING
{
}
}
MODULE system_timer
{
class = "altera_avalon_timer";
class_version = "2.1";
iss_model_name = "altera_avalon_timer";
SLAVE s1
{
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Is_Printable_Device = "0";
Address_Alignment = "native";
Address_Width = "3";
Data_Width = "16";
Has_IRQ = "1";
Read_Wait_States = "1";
Write_Wait_States = "0";
MASTERED_BY cpu/data_master
{
priority = "1";
}
IRQ_MASTER cpu/data_master
{
IRQ_Number = "1";
}
Base_Address = "0x00900800";
}
PORT_WIRING
{
PORT address
{
direction = "input";
type = "address";
width = "3";
}
PORT chipselect
{
direction = "input";
type = "chipselect";
width = "1";
}
PORT clk
{
direction = "input";
type = "clk";
width = "1";
}
PORT irq
{
direction = "output";
type = "irq";
width = "1";
}
PORT readdata
{
direction = "output";
type = "readdata";
width = "16";
}
PORT reset_n
{
direction = "input";
type = "reset_n";
width = "1";
}
PORT write_n
{
direction = "input";
type = "write_n";
width = "1";
}
PORT writedata
{
direction = "input";
type = "writedata";
width = "16";
}
}
}
SYSTEM_BUILDER_INFO
{
Instantiate_In_System_Module = "1";
Is_Enabled = "1";
Clock_Source = "clk";
View
{
Settings_Summary = "Timer with 1 ms timeout period.";
MESSAGES
{
}
Is_Collapsed = "1";
}
}
WIZARD_SCRIPT_ARGUMENTS
{
always_run = "0";
fixed_period = "0";
snapshot = "1";
period = "1";
period_units = "ms";
reset_output = "0";
timeout_pulse_output = "0";
mult = "0.001";
}
HDL_INFO
{
Precompiled_Simulation_Library_Files = "";
Simulation_HDL_Files = "";
Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/system_timer.v";
Synthesis_Only_Files = "";
}
PORT_WIRING
{
}
}
MODULE ext_flash
{
class = "altera_avalon_cfi_flash";
class_version = "1.1";
iss_model_name = "altera_avalon_flash";
HDL_INFO
{
}
SLAVE s1
{
PORT_WIRING
{
PORT data
{
width = "8";
is_shared = "1";
direction = "inout";
type = "data";
}
PORT address
{
width = "23";
is_shared = "1";
direction = "input";
type = "address";
}
PORT read_n
{
width = "1";
is_shared = "1";
direction = "input";
type = "read_n";
}
PORT write_n
{
width = "1";
is_shared = "0";
direction = "input";
type = "write_n";
}
PORT select_n
{
width = "1";
is_shared = "0";
direction = "input";
type = "chipselect_n";
}
}
WIZARD_SCRIPT_ARGUMENTS
{
class = "altera_avalon_cfi_flash";
Supports_Flash_File_System = "1";
flash_reference_designator = "";
}
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon_tristate";
Is_Nonvolatile_Storage = "1";
Is_Memory_Device = "1";
Address_Alignment = "dynamic";
Has_IRQ = "0";
Base_Address = "0x00000000";
Data_Width = "8";
Address_Width = "23";
Simulation_Num_Lanes = "1";
Convert_Xs_To_0 = "1";
Write_Wait_States = "160ns";
Read_Wait_States = "160ns";
Setup_Time = "40ns";
Hold_Time = "40ns";
Address_Span = "8388608";
MASTERED_BY ext_ram_bus/tristate_master
{
priority = "1";
}
IRQ_MASTER cpu/data_master
{
IRQ_Number = "NC";
}
Is_Base_Locked = "1";
}
}
SYSTEM_BUILDER_INFO
{
Make_Memory_Model = "1";
Is_Enabled = "1";
Instantiate_In_System_Module = "0";
View
{
MESSAGES
{
}
Is_Collapsed = "1";
}
Clock_Source = "clk";
}
WIZARD_SCRIPT_ARGUMENTS
{
Setup_Value = "40";
Wait_Value = "160";
Hold_Value = "40";
Timing_Units = "ns";
Unit_Multiplier = "1";
Size = "8388608";
MAKE
{
MACRO
{
EXT_FLASH_FLASHTARGET_ALT_SIM_PREFIX = "$(EXT_FLASH_FLASHTARGET_TMP1:0=)";
EXT_FLASH_FLASHTARGET_TMP1 = "$(ALT_SIM_OPTIMIZE:1=RUN_ON_HDL_SIMULATOR_ONLY_)";
}
MASTER cpu
{
MACRO
{
BOOT_COPIER = "boot_loader_cfi.srec";
CPU_CLASS = "altera_nios2";
CPU_RESET_ADDRESS = "0x800000";
}
}
TARGET delete_placeholder_warning
{
ext_flash
{
Command1 = "rm -f $(SIMDIR)/contents_file_warning.txt";
Is_Phony = "1";
Target_File = "do_delete_placeholder_warning";
}
}
TARGET flashfiles
{
ext_flash
{
Command1 = "@echo Post-processing to create $(notdir $@)";
Command2 = "elf2flash --input=$(ELF) --flash= --boot=$(shell $(QUARTUS_ROOTDIR)/sopc_builder/bin/find_sopc_component_dir $(CPU_CLASS))/$(BOOT_COPIER) --outfile=$(EXT_FLASH_FLASHTARGET_ALT_SIM_PREFIX)ext_flash.flash --sim_optimize=$(ALT_SIM_OPTIMIZE) --base=0x0 --end=0x7FFFFF --reset=$(CPU_RESET_ADDRESS) ";
Dependency = "$(ELF)";
Target_File = "$(EXT_FLASH_FLASHTARGET_ALT_SIM_PREFIX)ext_flash.flash";
}
}
TARGET sim
{
ext_flash
{
Command1 = "if [ ! -d $(SIMDIR) ]; then mkdir $(SIMDIR) ; fi";
Command2 = "@echo Hardware simulation is not enabled for the target SOPC Builder system. Skipping creation of hardware simulation model contents and simulation symbol files. \\(Note: This does not affect the instruction set simulator.\\)";
Command3 = "touch $(SIMDIR)/dummy_file";
Dependency = "$(ELF)";
Target_File = "$(SIMDIR)/dummy_file";
}
}
}
}
}
MODULE ext_ram
{
class = "altera_nios_dev_kit_stratix_edition_sram2";
class_version = "1.0";
iss_model_name = "altera_memory";
HDL_INFO
{
}
WIZARD_SCRIPT_ARGUMENTS
{
sram_memory_size = "1024";
sram_memory_units = "1024";
sram_data_width = "32";
MAKE
{
TARGET delete_placeholder_warning
{
ext_ram
{
Command1 = "rm -f $(SIMDIR)/contents_file_warning.txt";
Is_Phony = "1";
Target_File = "do_delete_placeholder_warning";
}
}
TARGET sim
{
ext_ram
{
Command1 = "if [ ! -d $(SIMDIR) ]; then mkdir $(SIMDIR) ; fi";
Command2 = "@echo Hardware simulation is not enabled for the target SOPC Builder system. Skipping creation of hardware simulation model contents and simulation symbol files. \\(Note: This does not affect the instruction set simulator.\\)";
Command3 = "touch $(SIMDIR)/dummy_file";
Dependency = "$(ELF)";
Target_File = "$(SIMDIR)/dummy_file";
}
}
}
}
SLAVE s1
{
PORT_WIRING
{
PORT data
{
width = "32";
is_shared = "1";
direction = "inout";
type = "data";
}
PORT address
{
width = "18";
is_shared = "1";
direction = "input";
type = "address";
}
PORT read_n
{
width = "1";
is_shared = "0";
direction = "input";
type = "read_n";
}
PORT write_n
{
width = "1";
is_shared = "0";
direction = "input";
type = "write_n";
}
PORT be_n
{
width = "4";
is_shared = "0";
direction = "input";
type = "byteenable_n";
}
PORT select_n
{
width = "1";
is_shared = "0";
direction = "input";
type = "chipselect_n";
}
}
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon_tristate";
Is_Memory_Device = "1";
Address_Alignment = "dynamic";
Data_Width = "32";
Address_Width = "18";
Has_IRQ = "0";
Read_Wait_States = "0ns";
Write_Wait_States = "0ns";
Hold_Time = "half";
Base_Address = "0x00800000";
Address_Span = "1048576";
MASTERED_BY ext_ram_bus/tristate_master
{
priority = "1";
}
IRQ_MASTER cpu/data_master
{
IRQ_Number = "NC";
}
Setup_Time = "0";
}
}
SYSTEM_BUILDER_INFO
{
Is_Enabled = "1";
Instantiate_In_System_Module = "0";
Make_Memory_Model = "1";
Default_Module_Name = "sram";
View
{
MESSAGES
{
}
Is_Collapsed = "1";
}
Clock_Source = "clk";
}
}
MODULE ext_ram_bus
{
class = "altera_avalon_tri_state_bridge";
class_version = "2.0";
SLAVE avalon_slave
{
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Bridges_To = "tristate_master";
Base_Address = "N/A";
Has_IRQ = "0";
IRQ = "N/A";
Register_Outgoing_Signals = "1";
Register_Incoming_Signals = "1";
MASTERED_BY cpu/instruction_master
{
priority = "1";
}
MASTERED_BY cpu/data_master
{
priority = "1";
}
IRQ_MASTER cpu/data_master
{
IRQ_Number = "NC";
}
}
}
MASTER tristate_master
{
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon_tristate";
Bridges_To = "avalon_slave";
}
}
SYSTEM_BUILDER_INFO
{
Instantiate_In_System_Module = "1";
Is_Enabled = "1";
Is_Bridge = "1";
Clock_Source = "clk";
View
{
MESSAGES
{
}
Is_Collapsed = "1";
}
}
}
MODULE button_pio
{
class = "altera_avalon_pio";
class_version = "2.2";
HDL_INFO
{
Precompiled_Simulation_Library_Files = "";
Simulation_HDL_Files = "";
Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/button_pio.v";
Synthesis_Only_Files = "";
}
PORT_WIRING
{
PORT in_port
{
direction = "input";
width = "4";
}
}
SLAVE s1
{
PORT_WIRING
{
PORT address
{
direction = "input";
type = "address";
width = "2";
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