📄 first_nios2_system.ptf
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CONSTANT nasys_dcache_line_size_log2
{
value = "2";
comment = "Log2 size in bytes of each dcache line";
}
}
license_status = "encrypted";
germs_monitor_id = "";
cpuid_sz = "1";
cpuid_value = "0";
}
SYSTEM_BUILDER_INFO
{
Parameters_Signature = "";
Is_CPU = "1";
Is_Enabled = "1";
Instantiate_In_System_Module = "1";
Required_Device_Family = "STRATIX,STRATIXII,CYCLONE,CYCLONEII";
Default_Module_Name = "cpu";
Clock_Source = "clk";
View
{
MESSAGES
{
}
Is_Collapsed = "1";
Settings_Summary = "Nios II/s
<br> 4-Kbyte Instruction Cache
<br> JTAG Debug Module
";
}
}
SOFTWARE_COMPONENT altera_plugs_library
{
class = "altera_plugs_library";
class_version = "2.1";
WIZARD_SCRIPT_ARGUMENTS
{
CONSTANTS
{
CONSTANT PLUGS_PLUG_COUNT
{
value = "5";
comment = "Maximum number of plugs";
}
CONSTANT PLUGS_ADAPTER_COUNT
{
value = "2";
comment = "Maximum number of adapters";
}
CONSTANT PLUGS_DNS
{
value = "1";
comment = "Have routines for DNS lookups";
}
CONSTANT PLUGS_PING
{
value = "1";
comment = "Respond to icmp echo (ping) messages";
}
CONSTANT PLUGS_TCP
{
value = "1";
comment = "Support tcp in/out connections";
}
CONSTANT PLUGS_IRQ
{
value = "1";
comment = "Run at interrupte level";
}
CONSTANT PLUGS_DEBUG
{
value = "1";
comment = "Support debug routines";
}
}
}
SYSTEM_BUILDER_INFO
{
Is_Enabled = "1";
}
}
PORT_WIRING
{
}
SIMULATION
{
DISPLAY
{
SIGNAL aaa
{
format = "Logic";
name = "i_readdata";
radix = "hexadecimal";
}
SIGNAL aab
{
format = "Logic";
name = "i_readdatavalid";
radix = "hexadecimal";
}
SIGNAL aac
{
format = "Logic";
name = "i_waitrequest";
radix = "hexadecimal";
}
SIGNAL aad
{
format = "Logic";
name = "i_address";
radix = "hexadecimal";
}
SIGNAL aae
{
format = "Logic";
name = "i_read";
radix = "hexadecimal";
}
SIGNAL aaf
{
format = "Logic";
name = "clk";
radix = "hexadecimal";
}
SIGNAL aag
{
format = "Logic";
name = "reset_n";
radix = "hexadecimal";
}
SIGNAL aah
{
format = "Logic";
name = "d_readdata";
radix = "hexadecimal";
}
SIGNAL aai
{
format = "Logic";
name = "d_waitrequest";
radix = "hexadecimal";
}
SIGNAL aaj
{
format = "Logic";
name = "d_irq";
radix = "hexadecimal";
}
SIGNAL aak
{
format = "Logic";
name = "d_address";
radix = "hexadecimal";
}
SIGNAL aal
{
format = "Logic";
name = "d_byteenable";
radix = "hexadecimal";
}
SIGNAL aam
{
format = "Logic";
name = "d_read";
radix = "hexadecimal";
}
SIGNAL aan
{
format = "Logic";
name = "d_write";
radix = "hexadecimal";
}
SIGNAL aao
{
format = "Logic";
name = "d_writedata";
radix = "hexadecimal";
}
SIGNAL aap
{
format = "Divider";
name = "base pipeline";
radix = "";
}
SIGNAL aaq
{
format = "Logic";
name = "clk";
radix = "hexadecimal";
}
SIGNAL aar
{
format = "Logic";
name = "reset_n";
radix = "hexadecimal";
}
SIGNAL aas
{
format = "Logic";
name = "M_stall";
radix = "hexadecimal";
}
SIGNAL aat
{
format = "Logic";
name = "F_pcb_nxt";
radix = "hexadecimal";
}
SIGNAL aau
{
format = "Logic";
name = "F_pcb";
radix = "hexadecimal";
}
SIGNAL aav
{
format = "Logic";
name = "D_pcb";
radix = "hexadecimal";
}
SIGNAL aaw
{
format = "Logic";
name = "E_pcb";
radix = "hexadecimal";
}
SIGNAL aax
{
format = "Logic";
name = "M_pcb";
radix = "hexadecimal";
}
SIGNAL aay
{
format = "Logic";
name = "W_pcb";
radix = "hexadecimal";
}
SIGNAL aaz
{
format = "Logic";
name = "F_vinst";
radix = "ascii";
}
SIGNAL aba
{
format = "Logic";
name = "D_vinst";
radix = "ascii";
}
SIGNAL abb
{
format = "Logic";
name = "E_vinst";
radix = "ascii";
}
SIGNAL abc
{
format = "Logic";
name = "M_vinst";
radix = "ascii";
}
SIGNAL abd
{
format = "Logic";
name = "W_vinst";
radix = "ascii";
}
SIGNAL abe
{
format = "Logic";
name = "F_inst_ram_hit";
radix = "hexadecimal";
}
SIGNAL abf
{
format = "Logic";
name = "F_issue";
radix = "hexadecimal";
}
SIGNAL abg
{
format = "Logic";
name = "F_kill";
radix = "hexadecimal";
}
SIGNAL abh
{
format = "Logic";
name = "D_kill";
radix = "hexadecimal";
}
SIGNAL abi
{
format = "Logic";
name = "D_refetch";
radix = "hexadecimal";
}
SIGNAL abj
{
format = "Logic";
name = "D_issue";
radix = "hexadecimal";
}
SIGNAL abk
{
format = "Logic";
name = "D_valid";
radix = "hexadecimal";
}
SIGNAL abl
{
format = "Logic";
name = "E_valid";
radix = "hexadecimal";
}
SIGNAL abm
{
format = "Logic";
name = "M_valid";
radix = "hexadecimal";
}
SIGNAL abn
{
format = "Logic";
name = "W_valid";
radix = "hexadecimal";
}
SIGNAL abo
{
format = "Logic";
name = "W_wr_dst_reg";
radix = "hexadecimal";
}
SIGNAL abp
{
format = "Logic";
name = "W_dst_regnum";
radix = "hexadecimal";
}
SIGNAL abq
{
format = "Logic";
name = "W_wr_data";
radix = "hexadecimal";
}
SIGNAL abr
{
format = "Logic";
name = "F_en";
radix = "hexadecimal";
}
SIGNAL abs
{
format = "Logic";
name = "D_en";
radix = "hexadecimal";
}
SIGNAL abt
{
format = "Logic";
name = "E_en";
radix = "hexadecimal";
}
SIGNAL abu
{
format = "Logic";
name = "M_en";
radix = "hexadecimal";
}
SIGNAL abv
{
format = "Logic";
name = "F_iw";
radix = "hexadecimal";
}
SIGNAL abw
{
format = "Logic";
name = "D_iw";
radix = "hexadecimal";
}
SIGNAL abx
{
format = "Logic";
name = "E_iw";
radix = "hexadecimal";
}
SIGNAL aby
{
format = "Logic";
name = "E_valid_prior_to_hbreak";
radix = "hexadecimal";
}
SIGNAL abz
{
format = "Logic";
name = "E_pipe_flush";
radix = "hexadecimal";
}
SIGNAL aca
{
format = "Logic";
name = "E_pipe_flush_baddr";
radix = "hexadecimal";
}
SIGNAL acb
{
format = "Logic";
name = "M_status_reg_pie";
radix = "hexadecimal";
}
SIGNAL acc
{
format = "Logic";
name = "M_ienable_reg";
radix = "hexadecimal";
}
SIGNAL acd
{
format = "Logic";
name = "intr_req";
radix = "hexadecimal";
}
}
}
}
MODULE jtag_uart
{
class = "altera_avalon_jtag_uart";
class_version = "1.0";
iss_model_name = "altera_avalon_jtag_uart";
SLAVE avalon_jtag_slave
{
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Is_Printable_Device = "1";
Address_Alignment = "native";
Address_Width = "1";
Data_Width = "32";
Has_IRQ = "1";
Read_Wait_States = "peripheral_controlled";
Write_Wait_States = "peripheral_controlled";
JTAG_Hub_Base_Id = "0x04006E";
JTAG_Hub_Instance_Id = "1";
MASTERED_BY cpu/data_master
{
priority = "1";
}
IRQ_MASTER cpu/data_master
{
IRQ_Number = "0";
}
Base_Address = "0x00900870";
}
PORT_WIRING
{
PORT clk
{
type = "clk";
direction = "input";
width = "1";
}
PORT rst_n
{
type = "reset_n";
direction = "input";
width = "1";
}
PORT av_chipselect
{
type = "chipselect";
direction = "input";
width = "1";
}
PORT av_address
{
type = "address";
direction = "input";
width = "1";
}
PORT av_read_n
{
type = "read_n";
direction = "input";
width = "1";
}
PORT av_readdata
{
type = "readdata";
direction = "output";
width = "32";
}
PORT av_write_n
{
type = "write_n";
direction = "input";
width = "1";
}
PORT av_writedata
{
type = "writedata";
direction = "input";
width = "32";
}
PORT av_waitrequest
{
type = "waitrequest";
direction = "output";
width = "1";
}
PORT av_irq
{
type = "irq";
direction = "output";
width = "1";
}
PORT dataavailable
{
direction = "output";
type = "dataavailable";
width = "1";
}
PORT readyfordata
{
direction = "output";
type = "readyfordata";
width = "1";
}
}
}
SYSTEM_BUILDER_INFO
{
Instantiate_In_System_Module = "1";
Is_Enabled = "1";
Iss_Launch_Telnet = "0";
Clock_Source = "clk";
View
{
Settings_Summary = "<br>Write Depth: 64; Write IRQ Threshold: 8
<br>Read Depth: 64; Read IRQ Threshold: 8";
MESSAGES
{
}
Is_Collapsed = "1";
}
}
WIZARD_SCRIPT_ARGUMENTS
{
write_depth = "64";
read_depth = "64";
write_threshold = "8";
read_threshold = "8";
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