📄 first_nios2_system.ptf
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SYSTEM first_nios2_system
{
System_Wizard_Version = "4.20";
System_Wizard_Build = "157";
WIZARD_SCRIPT_ARGUMENTS
{
device_family = "CYCLONE";
clock_freq = "50000000";
generate_hdl = "1";
generate_sdk = "0";
do_build_sim = "0";
board_class = "";
CLOCKS
{
clk = "50000000";
}
hdl_language = "verilog";
view_master_priorities = "0";
name_column_width = "150";
desc_column_width = "152";
bustype_column_width = "0";
base_column_width = "74";
clock_column_width = "72";
end_column_width = "74";
device_family_id = "CYCLONE";
view_master_columns = "";
view_frame_window = "maximized";
BOARD_INFO
{
altera_avalon_cfi_flash
{
reference_designators = "";
}
}
do_log_history = "0";
}
MODULE cpu
{
class = "altera_nios2";
class_version = "1.1";
iss_model_name = "altera_nios2";
HDL_INFO
{
PLI_Files = "";
Precompiled_Simulation_Library_Files = "";
Simulation_HDL_Files = "";
Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/cpu_test_bench.v, __PROJECT_DIRECTORY__/cpu_jtag_debug_module.v, __PROJECT_DIRECTORY__/cpu_jtag_debug_module_wrapper.v, __PROJECT_DIRECTORY__/cpu.v";
Synthesis_Only_Files = "";
}
MASTER instruction_master
{
PORT_WIRING
{
PORT i_address
{
direction = "output";
type = "address";
width = "24";
}
PORT i_read
{
direction = "output";
type = "read";
width = "1";
}
PORT i_readdata
{
direction = "input";
type = "readdata";
width = "32";
}
PORT i_readdatavalid
{
direction = "input";
type = "readdatavalid";
width = "1";
}
PORT i_waitrequest
{
direction = "input";
type = "waitrequest";
width = "1";
}
}
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Data_Width = "32";
Max_Address_Width = "31";
Address_Width = "8";
Is_Instruction_Master = "1";
Has_IRQ = "0";
Irq_Scheme = "individual_requests";
Interrupt_Range = "0-0";
Is_Enabled = "1";
}
}
MASTER data_master
{
PORT_WIRING
{
PORT clk
{
direction = "input";
type = "clk";
width = "1";
}
PORT d_address
{
direction = "output";
type = "address";
width = "24";
}
PORT d_byteenable
{
direction = "output";
type = "byteenable";
width = "4";
}
PORT d_irq
{
direction = "input";
type = "irq";
width = "32";
}
PORT d_read
{
direction = "output";
type = "read";
width = "1";
}
PORT d_readdata
{
direction = "input";
type = "readdata";
width = "32";
}
PORT d_waitrequest
{
direction = "input";
type = "waitrequest";
width = "1";
}
PORT d_write
{
direction = "output";
type = "write";
width = "1";
}
PORT d_writedata
{
direction = "output";
type = "writedata";
width = "32";
}
PORT jtag_debug_module_debugaccess_to_roms
{
direction = "output";
type = "debugaccess";
width = "1";
}
}
SYSTEM_BUILDER_INFO
{
Register_Incoming_Signals = "1";
Bus_Type = "avalon";
Data_Width = "32";
Max_Address_Width = "31";
Address_Width = "8";
Is_Data_Master = "1";
Has_IRQ = "1";
Irq_Scheme = "individual_requests";
Interrupt_Range = "0-31";
Is_Enabled = "1";
}
}
MASTER data_master2
{
PORT_WIRING
{
}
SYSTEM_BUILDER_INFO
{
Register_Incoming_Signals = "1";
Bus_Type = "avalon";
Data_Width = "32";
Max_Address_Width = "31";
Address_Width = "8";
Is_Data_Master = "1";
Has_IRQ = "0";
Is_Enabled = "0";
}
}
MASTER tightly_coupled_data_master_0
{
PORT_WIRING
{
}
SYSTEM_BUILDER_INFO
{
Register_Incoming_Signals = "0";
Bus_Type = "avalon";
Data_Width = "32";
Max_Address_Width = "31";
Address_Width = "8";
Is_Data_Master = "1";
Has_IRQ = "0";
Is_Enabled = "0";
Connection_Limit = "1";
Is_Channel = "1";
}
}
MASTER tightly_coupled_data_master_1
{
PORT_WIRING
{
}
SYSTEM_BUILDER_INFO
{
Register_Incoming_Signals = "0";
Bus_Type = "avalon";
Data_Width = "32";
Max_Address_Width = "31";
Address_Width = "8";
Is_Data_Master = "1";
Has_IRQ = "0";
Is_Enabled = "0";
Connection_Limit = "1";
Is_Channel = "1";
}
}
MASTER tightly_coupled_data_master_2
{
PORT_WIRING
{
}
SYSTEM_BUILDER_INFO
{
Register_Incoming_Signals = "0";
Bus_Type = "avalon";
Data_Width = "32";
Max_Address_Width = "31";
Address_Width = "8";
Is_Data_Master = "1";
Has_IRQ = "0";
Is_Enabled = "0";
Connection_Limit = "1";
Is_Channel = "1";
}
}
MASTER tightly_coupled_data_master_3
{
PORT_WIRING
{
}
SYSTEM_BUILDER_INFO
{
Register_Incoming_Signals = "0";
Bus_Type = "avalon";
Data_Width = "32";
Max_Address_Width = "31";
Address_Width = "8";
Is_Data_Master = "1";
Has_IRQ = "0";
Is_Enabled = "0";
Connection_Limit = "1";
Is_Channel = "1";
}
}
MASTER tightly_coupled_instruction_master_0
{
PORT_WIRING
{
}
SYSTEM_BUILDER_INFO
{
Register_Incoming_Signals = "0";
Bus_Type = "avalon";
Data_Width = "32";
Max_Address_Width = "31";
Address_Width = "8";
Is_Instruction_Master = "1";
Has_IRQ = "0";
Is_Enabled = "0";
Connection_Limit = "1";
Is_Channel = "1";
}
}
MASTER custom_instruction_master
{
PORT_WIRING
{
}
SYSTEM_BUILDER_INFO
{
Bus_Type = "nios_custom_instruction";
Data_Width = "32";
Address_Width = "8";
Max_Address_Width = "8";
Base_Address = "N/A";
Is_Visible = "0";
Is_Custom_Instruction = "0";
Is_Enabled = "0";
}
}
SLAVE jtag_debug_module
{
PORT_WIRING
{
PORT jtag_debug_module_address
{
direction = "input";
type = "address";
width = "9";
}
PORT jtag_debug_module_begintransfer
{
direction = "input";
type = "begintransfer";
width = "1";
}
PORT jtag_debug_module_byteenable
{
direction = "input";
type = "byteenable";
width = "4";
}
PORT jtag_debug_module_clk
{
direction = "input";
type = "clk";
width = "1";
}
PORT jtag_debug_module_debugaccess
{
direction = "input";
type = "debugaccess";
width = "1";
}
PORT jtag_debug_module_readdata
{
direction = "output";
type = "readdata";
width = "32";
}
PORT jtag_debug_module_reset
{
direction = "input";
type = "reset";
width = "1";
}
PORT jtag_debug_module_resetrequest
{
direction = "output";
type = "resetrequest";
width = "1";
}
PORT jtag_debug_module_select
{
direction = "input";
type = "chipselect";
width = "1";
}
PORT jtag_debug_module_write
{
direction = "input";
type = "write";
width = "1";
}
PORT jtag_debug_module_writedata
{
direction = "input";
type = "writedata";
width = "32";
}
PORT reset_n
{
direction = "input";
type = "reset_n";
width = "1";
}
}
SYSTEM_BUILDER_INFO
{
Read_Wait_States = "1";
Write_Wait_States = "1";
Register_Incoming_Signals = "1";
Bus_Type = "avalon";
Data_Width = "32";
Address_Width = "9";
Accepts_Internal_Connections = "1";
Requires_Internal_Connections = "instruction_master,data_master";
Accepts_External_Connections = "0";
Is_Enabled = "1";
Address_Alignment = "dynamic";
Base_Address = "0x00900000";
Is_Memory_Device = "1";
Is_Printable_Device = "0";
Uses_Tri_State_Data_Bus = "0";
Has_IRQ = "0";
JTAG_Hub_Base_Id = "593990";
JTAG_Hub_Instance_Id = "1";
MASTERED_BY cpu/instruction_master
{
priority = "1";
}
MASTERED_BY cpu/data_master
{
priority = "1";
}
IRQ_MASTER cpu/data_master
{
IRQ_Number = "NC";
}
}
}
WIZARD_SCRIPT_ARGUMENTS
{
asp_debug = "0";
asp_core_debug = "0";
CPU_Architecture = "nios2";
do_generate = "1";
cpu_selection = "s";
CPU_Implementation = "small";
cache_has_dcache = "0";
cache_has_icache = "1";
cache_dcache_size = "2048";
cache_icache_size = "4096";
include_debug = "0";
include_trace = "0";
include_oci = "1";
include_third_party_debug_port = "0";
debug_level = "2";
oci_offchip_trace = "0";
oci_onchip_trace = "0";
oci_data_trace = "0";
oci_trace_addr_width = "7";
oci_num_xbrk = "0";
oci_num_dbrk = "0";
oci_dbrk_trace = "0";
oci_dbrk_pairs = "0";
oci_num_pm = "0";
oci_pm_width = "40";
oci_debugreq_signals = "0";
oci_trigger_arming = "1";
hardware_multiply_present = "0";
hardware_divide_present = "0";
gui_hardware_multiply_setting = "no_mul_small_le_shift";
hardware_multiply_uses_les = "0";
hardware_multiply_omits_msw = "1";
hardware_multiply_impl = "no_mul";
reset_slave = "ext_ram/s1";
reset_offset = "0x00000000";
exc_slave = "ext_ram/s1";
exc_offset = "0x00000020";
break_slave = "cpu/jtag_debug_module";
break_offset = "0x00000020";
break_slave_override = "";
break_offset_override = "0x20";
legacy_sdk_support = "0";
altera_show_unreleased_features = "0";
full_waveform_signals = "0";
illegal_instructions_trap = "0";
cache_omit_dcache = "0";
cache_omit_icache = "0";
omit_instruction_master = "0";
omit_data_master = "0";
num_tightly_coupled_data_masters = "0";
num_tightly_coupled_instruction_masters = "0";
gui_branch_prediction_type = "Automatic";
branch_prediction_type = "Static";
bht_ptr_sz = "8";
bht_index_pc_only = "0";
shift_rot_impl = "small_le_shift";
altera_internal_test = "0";
performance_counters_present = "0";
performance_counters_width = "32";
ras_ptr_sz = "4";
jtb_ptr_sz = "5";
ibuf_ptr_sz = "4";
always_encrypt = "1";
activate_model_checker = "0";
activate_monitors = "1";
activate_test_end_checker = "0";
activate_trace = "1";
clear_x_bits_ld_non_bypass = "1";
bit_31_bypass_dcache = "1";
always_bypass_dcache = "0";
hdl_sim_caches_cleared = "1";
consistent_synthesis = "0";
hbreak_test = "0";
allow_full_address_range = "0";
iss_trace_on = "0";
iss_trace_warning = "1";
iss_trace_info = "1";
iss_trace_disassembly = "0";
iss_trace_registers = "0";
iss_trace_instr_count = "0";
iss_software_debug = "0";
iss_software_debug_port = "9996";
iss_memory_dump_start = "";
iss_memory_dump_end = "";
Boot_Copier = "boot_loader_cfi.srec";
Boot_Copier_EPCS = "boot_loader_epcs.srec";
CONSTANTS
{
CONSTANT __nios_catch_irqs__
{
value = "1";
comment = "Include panic handler for all irqs (needs uart)";
}
CONSTANT __nios_use_constructors__
{
value = "1";
comment = "Call c++ static constructors";
}
CONSTANT __nios_use_small_printf__
{
value = "1";
comment = "Smaller non-ANSI printf, with no floating point";
}
CONSTANT nasys_has_icache
{
value = "1";
comment = "True if instruction cache present";
}
CONSTANT nasys_icache_size
{
value = "4096";
comment = "Size in bytes of instruction cache";
}
CONSTANT nasys_icache_line_size
{
value = "32";
comment = "Size in bytes of each icache line";
}
CONSTANT nasys_icache_line_size_log2
{
value = "5";
comment = "Log2 size in bytes of each icache line";
}
CONSTANT nasys_has_dcache
{
value = "1";
comment = "True if instruction cache present";
}
CONSTANT nasys_dcache_size
{
value = "2048";
comment = "Size in bytes of data cache";
}
CONSTANT nasys_dcache_line_size
{
value = "4";
comment = "Size in bytes of each dcache line";
}
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