div16.vhd

我的课程设计

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity div16 is
       port(clk    : in std_logic;     
            clk_div: inout std_logic);
end div16;

architecture rtl of div16 is
        signal count : std_logic_vector(3 downto 0);
	

begin

      process(clk)
      begin
            if(clk'event and clk = '1') then        
                if (count = "1111") then
                   count   <= (others =>  '0'); 
					clk_div<= not clk_div;
                else
                   count   <= count +1;
                end if;
            end if;
 	   end process;
       
  end rtl;