div.vhd

来自「我的课程设计」· VHDL 代码 · 共 42 行

library ieee;
use ieee.std_logic_arith.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity div is
 port(clk:in std_logic;
		clk_out:inout std_logic
		);
end div;

architecture behave of div is
signal div1,div2,div3:std_logic;

component div16
port(clk:in std_logic;
		clk_div:inout std_logic
		);
end component;

component div8
port(clk:in std_logic;
		clk_div:inout std_logic
		);
end component;



 begin
  

u0:div16
	port map(clk,div1);
u1:div16
	port map(div1,div2);
u2:div16
	port map(div2,div3);
u1:div8
	port map(div3,clk_out);


end behave;