syslib.c

标准arm vxworks bsp 模板

/* sysLib.c - template ARM Integrator system-dependent routines */

/* Copyright 2002 Wind River Systems, Inc. */

#include "copyright_wrs.h"


/*
TODO -  Remove the template modification history and begin a new history
        starting with version 01a and growing the history upward with
        each revision.

modification history
--------------------
01b,17jul02,dat  remove obsolete information
01a,23may02,scm  written
*/

/*
DESCRIPTION
This library provides board-specific routines.  The chip drivers included are:

    templateSio.c - template SIO driver
    templateTimer.c - Zilog Z8536 timer library (auxiliary clock)
    nullNvRam.c - byte-oriented generic non-volatile RAM library
    nullVme.c - byte-oriented generic non-volatile RAM library
    templateIntrCtl.c - template interrrupt controller device

INCLUDE FILES: sysLib.h

SEE ALSO:
.pG "Configuration"
.I "ARM Architecture Reference Manual,"
.I "ARM 7TDMI Data Sheet,"
.I "ARM 720T Data Sheet,"
.I "ARM 740T Data Sheet,"
.I "ARM 920T Technical Reference Manual",
.I "ARM 940T Technical Reference Manual",
.I "ARM 946E-S Technical Reference Manual",
.I "ARM 966E-S Technical Reference Manual",
.I "ARM Reference Peripherals Specification,"
.I "ARM Integrator/AP User Guide",
.I "ARM Integrator/CM7TDMI User Guide",
.I "ARM Integrator/CM720T User Guide",
.I "ARM Integrator/CM740T User Guide",
.I "ARM Integrator/CM920T User Guide",
.I "ARM Integrator/CM940T User Guide",
.I "ARM Integrator/CM946E User Guide",
.I "ARM Integrator/CM9x6ES Datasheet".
*/

/* includes */

#include "vxWorks.h"
#include "config.h"

#include "sysLib.h"
#include "string.h"
#include "intLib.h"
#include "taskLib.h"
#include "vxLib.h"
#include "muxLib.h"
#include "cacheLib.h"
#if defined(CPU_720T)  || defined(CPU_720T_T) || \
    defined(CPU_740T)  || defined(CPU_740T_T) || \
    defined(CPU_920T)  || defined(CPU_920T_T) || \
    defined(CPU_940T)  || defined(CPU_940T_T) || \
    defined(CPU_946ES) || defined(CPU_946ES_T)
#include "arch/arm/mmuArmLib.h"
#include "private/vmLibP.h"
#include "dllLib.h"
#ifdef INCLUDE_PCI
#include "pciIomapLib.h"
#endif
#endif /* defined(720T/740T/920T/940T/946ES) */

#ifdef INCLUDE_UGL2_0
#define INCLUDE_AMBAKEYBOARD
#define INCLUDE_AMBAMOUSE
#endif

/* imports */

IMPORT char end [];			    /* end of system, created by ld */
IMPORT VOIDFUNCPTR _func_armIntStackSplit;  /* ptr to fn to split stack */



#if !defined(INCLUDE_MMU) && \
    (defined(INCLUDE_CACHE_SUPPORT) || defined(INCLUDE_MMU_BASIC) || \
     defined(INCLUDE_MMU_FULL) || defined(INCLUDE_MMU_MPU))
#define INCLUDE_MMU
#endif

#if defined(INCLUDE_CACHE_SUPPORT)
#if defined(CPU_7TDMI) || defined(CPU_7TDMI_T) || \
    defined(CPU_966ES) || defined(CPU_966ES_T)
       FUNCPTR sysCacheLibInit = NULL;
#endif /* defined(CPU_7TDMI/7TDMI_T) */

#if     defined(CPU_940T) || defined(CPU_940T_T)
UINT32 * sysCacheUncachedAdrs = (UINT32 *)SYS_CACHE_UNCACHED_ADRS;
#endif /* defined(CPU_940T/940T_T) */
#endif /* defined(INCLUDE_CACHE_SUPPORT) */


/* globals */

#if defined(INCLUDE_MMU)
/*
 * sysPhysMemDesc[] is used to initialize the Page Table Entry (PTE) array
 * used by the MMU to translate addresses with single page (4k) granularity.
 * PTE memory space should not, in general, overlap BAT memory space but
 * may be allowed if only Data or Instruction access is mapped via BAT.
 *
 * Address translations for local RAM, memory mapped PCI bus, memory mapped
 * VME A16 space and local PROM/FLASH are set here.
 *
 * PTEs are held, strangely enough, in a Page Table.  Page Table sizes are
 * integer powers of two based on amount of memory to be mapped and a
 * minimum size of 64 kbytes.  The MINIMUM recommended Page Table sizes
 * for 32-bit PowerPCs are:
 *
 * Total mapped memory          Page Table size
 * -------------------          ---------------
 *        8 Meg                      64 K
 *       16 Meg                     128 K
 *       32 Meg                     256 K
 *       64 Meg                     512 K
 *      128 Meg                       1 Meg
 *      .                               .
 *      .                               .
 *      .                               .
 *
 * [Ref: chapter 7, PowerPC Microprocessor Family: The Programming Environments]
 *
 * The following structure describes the various different parts of the
 * memory map to be used only during initialisation by
 * vm(Base)GlobalMapInit() when INCLUDE_MMU_BASIC/FULL are
 * defined.
 *
 * Clearly, this structure is only needed if the CPU has an MMU!
 *
 * The following are not the smallest areas that could be allocated for a
 * working system. If the amount of memory used by the page tables is
 * critical, they could be reduced.
 *
 * The following structure describes the various different regions of the
 * memory map to be used only during initialisation by
 * vmMpuGlobalMapInit() when INCLUDE_MMU_MPU is defined.
 *
 * On the MPUs, the virtual and physical addresses must be
 * the same.  In addition, the regions must have an alignment equal to
 * their size, with a minimum size of 4K.  This restriction is very
 * important in understanding the region definitions.  Regions cannot be
 * arbitrarily moved or their size changed without considering
 * alignment.  There is no page-table RAM overhead to mapping in large
 * areas of the memory map, but we can only define 8 memory regions in
 * total. Regions cannot be marked as read-only in VxWorks.
 *
 * Here, we (arbitrarily) choose to leave as many regions in the MPU
 * unused as possible, so that they are available for later use (e.g. to
 * mark areas of RAM as non-cacheable).  This means that large areas are
 * mapped in as valid where no memory or I/O devices are actually
 * present.  If this is not desired, larger numbers of smaller regions
 * could be defined which more closely match what is actually present in
 * the memory map (paying close attention to the alignment requirements
 * mentioned above).  Spurious accesses outside those defined regions
 * would then cause access violation exceptions when the MPU is switched
 * on.
 *
 * Note that potentially important areas of memory space are currently
 * unmapped.  Core module alias areas, and the EBI space
 * (Boot ROM and SSRAM) are not defined, and will therefore cause
 * access violations.
 */
PHYS_MEM_DESC sysPhysMemDesc [] =
    {
    /*
     * Map the peripheral register area as writable but not cached or
     * buffered.
     */

    /*
     * TODO: Add/Remove additional mappings as needed to support special PCI
     * functions like memory mapped configuration space, or special IACK
     * register space.
     */

    {
    (void *) ARMBSP_PERIPHERAL_BASE,	/* virtual address */
    (void *) ARMBSP_PERIPHERAL_BASE,	/* physical address */

    /* Region must have alignment equal to size, minimum of PAGE_SIZE */

    ROUND_UP(ARMBSP_PERIPHERAL_SIZE, PAGE_SIZE),	/* length */

    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
    VM_STATE_VALID	| VM_STATE_WRITABLE	 | VM_STATE_CACHEABLE_NOT
    },

    /*
     * Main RAM region from 0 to max(SSRAM,SDRAM), marked cacheable and
     * bufferable.
     */
    {
    (void *) 0,	/* virtual address */
    (void *) 0,	/* physical address */

    /* Region must have alignment equal to size, minimum of PAGE_SIZE */

    ROUND_UP ((LOCAL_MEM_SIZE + LOCAL_MEM_LOCAL_ADRS), PAGE_SIZE), /* length */

    /* initial state: */

    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
    VM_STATE_VALID	| VM_STATE_WRITABLE	 | VM_STATE_CACHEABLE
    },

#if (LOCAL_MEM_LOCAL_ADRS != 0)
    /* If (e.g. on 946ES) we have image starting above where the
     * tightly-coupled memory is, then put another entry (higher priority than
     * the one before), which marks the area taken up by the tightly-coupled
     * memory as non-cacheable.
     */

    /* on-header SSRAM, or tightly-coupled memory */
    {
    (void *) 0,			/* virtual address */
    (void *) 0,			/* physical address */
    ROUND_UP (LOCAL_MEM_LOCAL_ADRS, PAGE_SIZE), /* length, then initial state */
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
    VM_STATE_VALID	| VM_STATE_WRITABLE	 | VM_STATE_CACHEABLE_NOT
    },
#endif /* (LOCAL_MEM_LOCAL_ADRS != 0) */

    /*
     * Flash memory: marked valid and writeable but not cached -
     * we need to be able to poll words in the Flash when updating
     * contents.
     */
    {
    (void *) ROM_BASE_ADRS,	/* virtual address */
    (void *) ROM_BASE_ADRS,	/* physical address */

    ROUND_UP (ROM_SIZE_TOTAL, PAGE_SIZE),	/* length */

    /* initial state: */

    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT
    },

    /* I/O space: */

#ifdef INCLUDE_PCI
    {
    (void *) ARMBSP_PCI_BASE,
    (void *) ARMBSP_PCI_BASE,
    ROUND_UP (0x20000000, PAGE_SIZE),
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
    VM_STATE_VALID	| VM_STATE_WRITABLE	 | VM_STATE_CACHEABLE_NOT
    },
    {
    (void *) CPU_PCI_IO_ADRS,
    (void *) CPU_PCI_IO_ADRS,
    ROUND_UP (0x4000000, PAGE_SIZE),
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
    VM_STATE_VALID	| VM_STATE_WRITABLE	 | VM_STATE_CACHEABLE_NOT
    }
#endif
    };

int sysPhysMemDescNumEnt = NELEMENTS (sysPhysMemDesc);

#endif /* defined(INCLUDE_MMU) */

int	sysBus	    = BUS;		/* system bus type (VME_BUS, etc) */
int	sysCpu	    = CPU;		/* system CPU type (e.g. ARMARCH4/4_T)*/
char *	sysBootLine = BOOT_LINE_ADRS; 	/* address of boot line */
char *	sysExcMsg   = EXC_MSG_ADRS;	/* catastrophic message area */
int	sysProcNum;			/* processor number of this CPU */
int	sysFlags;			/* boot flags */
char	sysBootHost [BOOT_FIELD_LEN];	/* name of host from which we booted */
char	sysBootFile [BOOT_FIELD_LEN];	/* name of file from which we booted */

/* locals */

/* defines */

/* externals */

IMPORT int  ambaIntDevInit (void);
IMPORT void sysIntStackSplit (char *, long);

/* globals */

/* forward LOCAL functions declarations */

/* forward declarations */

char *	sysPhysMemTop (void);

#if defined (INCLUDE_USB)
void sysUsbPciInit(void);
#endif

/* included source files */

#include "mem/nullNvRam.c"
#include "vme/nullVme.c"
#include "timer/templateTimer.c"

#include "sysSerial.c"

/*******************************************************************************
*
* sysModel - return the model name of the CPU board
*
* This routine returns the model name of the CPU board.
*
* NOTE
* This routine does not include all of the possible variants, and the
* inclusion of a variant in here does not mean that it is supported.
*
* RETURNS: A pointer to a string identifying the board and CPU.
*/

char *sysModel (void)
    {
    return	"Model-1 (ARM)";
    }

/*******************************************************************************
*
* sysBspRev - return the BSP version with the revision eg 1.2/<x>
*
* This function returns a pointer to a BSP version with the revision.
* e.g. 1.2/<x>. BSP_REV is concatenated to BSP_VERSION to form the
* BSP identification string.
*
* RETURNS: A pointer to the BSP version/revision string.
*/

char * sysBspRev (void)
    {
    return (BSP_VERSION BSP_REV);
    }

/*******************************************************************************
*
* sysHwInit0 - perform early BSP-specific initialisation
*
* This routine performs such BSP-specific initialisation as is necessary before
* the architecture-independent cacheLibInit can be called. It is called
* from usrInit() before cacheLibInit(), before sysHwInit() and before BSS
* has been cleared.
*
* RETURNS: N/A
*/

void sysHwInit0 (void)
    {

#ifdef INCLUDE_CACHE_SUPPORT

    /*
     * TODO -
     * Install the appropriate cache library, no address translation
     * routines are required for this BSP, as the default memory map has
     * virtual and physical addresses the same.