template.h

标准arm vxworks bsp 模板

/* template.h - template board header */

/* Copyright 2002 Wind River Systems, Inc. */

/*
TODO -  Remove the template modification history and begin a new history
        starting with version 01a and growing the history upward with
        each revision.

modification history
--------------------
01b,17jul02,dat  remove obsolete information
01a,23may02,scm  written
*/

/*
This file contains I/O address and related constants for the ARM
BSP.
*/


/* TODO -Modify as needed... */


#ifndef	INCtemplateh
#define	INCtemplateh

#ifdef __cplusplus
extern "C" {
#endif

#define TARGET_ARMBSP

/* Flash definitions */

#define FLASH_BASE		0x10000000	/* Base address of Flash part */
#define FLASH_BLOCK_NUM		128		/* 128 kB block used as NVRAM */
#define FLASH_ADRS		(FLASH_BASE + (FLASH_BLOCK_NUM * 0x20000))
#define ARMBSP_FLASH_SIZE 	0x01000000 	/* Total Flash available. */
#define FLASH_WIDTH		2	  	/* one 16-bit wide parts */
#define FLASH_CHIP_WIDTH        2
#define FLASH_WIDTH_SPECIAL_2			/* see flash28.h */
#define SYS_FLASH_WRITE				/* use enable/disable routines*/

/*
 * It is not necessary to define SYS_FLASH_TYPE as FLASH_28F320 as
 * auto-identification correctly identifies the Flash part.
 */


/* BSP memory map */

#define ARMBSP_PERIPHERAL_BASE	0xF0000000
#define ARMBSP_PERIPHERAL_SIZE	0x10000000

#define ARMBSP_BOOT_ROM_LO          0x10040000
#define ARMBSP_BOOT_ROM_HI          0x11000000
#define ARMBSP_BOOT_ROM_BASE        ARMBSP_BOOT_ROM_LO
#define ARMBSP_BOOT_ROM_SIZE		0x00400000

/*  SDRAM is a DIMM therefore the size is not known. */

#define ARMBSP_SDRAM_BASE           0x20000000

/*#define ARMBSP_SDRAM_ALIAS_BASE     0x80000000
*/
/* RAM base in reset memory map */

/*#define ARMBSP_RESET_RAM_BASE	0x28000000
*/
/* PCI Base area */
/*
#define ARMBSP_PCI_BASE		0x40000000
#define ARMBSP_PCI_SIZE		0x3FFFFFFF

#define BUS		BUS_TYPE_PCI
*/

/* Signals generated from BSP clock generator. */

#define ARMBSP_SYSCLK   20000000		/* System bus clock */
#define ARMBSP_P_CLK    33000000		/* PCI clock */
#define ARMBSP_UARTCLK  14745600		/* UART clock */
#define ARMBSP_CLK24MHZ 24000000		/* KMI/Timer clock */


#define FL_SC_CONTROL			0x06	/* Enable Flash Write and Vpp */


/* - Hard coded id of the core module we are compiling for. */

#define CORE_MODULE 0

/*
 * interrupt control stuff
 * Note: FIQ is not handled within VxWorks so this is just IRQ
 */

#define IC_BASE 	(0x14000000 + (CORE_MODULE * 0x40))
#define IRQ_STATUS	(IC_BASE+0x000)	/* Read */
#define IRQ_RAW_STATUS	(IC_BASE+0x004)	/* Read */
#define IRQ_ENABLE	(IC_BASE+0x008)	/* Read/Write */
#define IRQ_DISABLE	(IC_BASE+0x00C)	/* Write */
#define IRQ_SOFT	(IC_BASE+0x010)	/* Read/Write */
#define IRQ_SOFTCLR     (IC_BASE+0x014) /* Write */
#define FIQ_STATUS	(IC_BASE+0x020)	/* Read */
#define FIQ_RAW_STATUS	(IC_BASE+0x024)	/* Read */
#define FIQ_ENABLE	(IC_BASE+0x028)	/* Read/Write */
#define FIQ_DISABLE	(IC_BASE+0x02C)	/* Write */

#define AMBA_INT_NUM_LEVELS	22
#define AMBA_INT_CSR_PEND	IRQ_STATUS
#define AMBA_INT_CSR_ENB	IRQ_ENABLE
#define AMBA_INT_CSR_DIS	IRQ_DISABLE
#define AMBA_INT_CSR_MASK	0x003FFFFF /* Mask out invalid status bits */


/* Interrupt levels */

#define INT_LVL_SOFT		0	/* soft interrupt */
#define INT_LVL_UART_0  	1	/* UART 0 */
#define INT_LVL_UART_1		2	/* UART 1 */
#define INT_LVL_KEYBOARD	3	/* keyboard interrupt */
#define INT_LVL_MOUSE		4	/* mouse interrupt */
#define INT_LVL_TIMER_0		5	/* timer 0 */
#define INT_LVL_TIMER_1		6	/* timer 1 */
#define INT_LVL_TIMER_2		7	/* timer 2 */
#define INT_LVL_RTC		8	/* real-time clock */
#define INT_LVL_EXP0		9	/* logic module 0 */
#define INT_LVL_EXP1		10	/* logic module 1 */
#define INT_LVL_EXP2		11	/* logic module 2 */
#define INT_LVL_EXP3		12	/* logic module 3 */
#define INT_LVL_PCI_0		13	/* PCI int A */
#define INT_LVL_PCI_1		14	/* PCI int B */
#define INT_LVL_PCI_2		15	/* PCI int C */
#define INT_LVL_PCI_3		16	/* PCI int D */
#define INT_LVL_PCIBRIDGE	17	/* V3 PCI bridge interrupt */
#define INT_LVL_DEG		18	/* CompactPCI aux (DEG#) */
#define INT_LVL_ENUM		19	/* CompactPCI aux (ENUM#) */
#define INT_LVL_PCILB		20	/* PCI local bus fault */
#define INT_LVL_APC		21	/* AutoPC external int */


/* interrupt vectors */

#define INT_VEC_SOFT		IVEC_TO_INUM(INT_LVL_SOFT)
#define INT_VEC_UART_0		IVEC_TO_INUM(INT_LVL_UART_0)
#define INT_VEC_UART_1		IVEC_TO_INUM(INT_LVL_UART_1)
#define INT_VEC_KEYBOARD	IVEC_TO_INUM(INT_LVL_KEYBOARD)
#define INT_VEC_MOUSE		IVEC_TO_INUM(INT_LVL_MOUSE)
#define INT_VEC_TIMER_0		IVEC_TO_INUM(INT_LVL_TIMER_0)
#define INT_VEC_TIMER_1		IVEC_TO_INUM(INT_LVL_TIMER_1)
#define INT_VEC_TIMER_2		IVEC_TO_INUM(INT_LVL_TIMER_2)
#define INT_VEC_RTC		IVEC_TO_INUM(INT_LVL_RTC)
#define INT_VEC_EXP0		IVEC_TO_INUM(INT_LVL_EXP0)
#define INT_VEC_EXP1		IVEC_TO_INUM(INT_LVL_EXP1)
#define INT_VEC_EXP2		IVEC_TO_INUM(INT_LVL_EXP2)
#define INT_VEC_EXP3		IVEC_TO_INUM(INT_LVL_EXP3)
#define INT_VEC_PCI_0		IVEC_TO_INUM(INT_LVL_PCI_0)
#define INT_VEC_PCI_1		IVEC_TO_INUM(INT_LVL_PCI_1)
#define INT_VEC_PCI_2		IVEC_TO_INUM(INT_LVL_PCI_2)
#define INT_VEC_PCI_3		IVEC_TO_INUM(INT_LVL_PCI_3)
#define INT_VEC_PCIBRIDGE	IVEC_TO_INUM(INT_LVL_PCIBRIDGE)
#define INT_VEC_DEG		IVEC_TO_INUM(INT_LVL_DEG)
#define INT_VEC_ENUM		IVEC_TO_INUM(INT_LVL_ENUM)
#define INT_VEC_PCILB		IVEC_TO_INUM(INT_LVL_PCILB)
#define INT_VEC_APC		IVEC_TO_INUM(INT_LVL_APC)


/* definitions for the AMBA UART */

#define UART_XTAL_FREQ		ARMBSP_UARTCLK /* UART baud rate clk freq */
#define N_SIO_CHANNELS		N_AMBA_UART_CHANNELS
#define N_UART_CHANNELS		N_AMBA_UART_CHANNELS
#define N_AMBA_UART_CHANNELS	2		/* number of AMBA UART chans */

#define UART_0_BASE_ADR		0x16000000	/* UART 0 base address */
#define UART_1_BASE_ADR		0x17000000	/* UART 1 base address */

/* definitions for the keyboard */
#define KBD_BASE_ADR		0x18000000	/* Keyboard 0 base address */
#define MOUSE_BASE_ADR		0x19000000	/* Mouse 1 base address */

#define KBD_REGS_SIZE           0x14
#define MOUSE_REGS_SIZE         0x14

/* definitions for the AMBA Timer */

#define AMBA_TIMER_BASE		0x13000000	/* Address of base of timer */
#define AMBA_BASE_OFFSET        0X100


#define AMBA_TIMER0_BASE ((AMBA_TIMER_BASE))
#define AMBA_TIMER1_BASE ((AMBA_TIMER_BASE) + AMBA_BASE_OFFSET)
#define AMBA_TIMER2_BASE ((AMBA_TIMER_BASE) + 2 * AMBA_BASE_OFFSET)

#define SYS_TIMER_BASE AMBA_TIMER0_BASE
#define AUX_TIMER_BASE AMBA_TIMER1_BASE

#define SYS_TIMER_INT_LVL (INT_LVL_TIMER_0)
#define AUX_TIMER_INT_LVL (INT_LVL_TIMER_1)

/* Add corresponding INT_VEC definitions for intConnect calls. */

#define SYS_TIMER_INT_VEC (INT_VEC_TIMER_0)
#define AUX_TIMER_INT_VEC (INT_VEC_TIMER_1)

#define AMBA_TIMER_SYS_TC_DISABLE	(TC_DISABLE | TC_PERIODIC | TC_DIV16)
#define AMBA_TIMER_SYS_TC_ENABLE	(TC_ENABLE  | TC_PERIODIC | TC_DIV16)
#define AMBA_TIMER_AUX_TC_DISABLE	(TC_DISABLE | TC_PERIODIC | TC_DIV16)
#define AMBA_TIMER_AUX_TC_ENABLE	(TC_ENABLE  | TC_PERIODIC | TC_DIV16)

/* Frequency of counter/timers */

#define SYS_TIMER_CLK	(ARMBSP_SYSCLK/16)
#define AUX_TIMER_CLK	(ARMBSP_CLK24MHZ/16)

#define AMBA_RELOAD_TICKS	0	/* No overhead */

/* Mask out unused bits from timer register. */

#define AMBA_TIMER_VALUE_MASK	0xFFFF

/* Sys Clk is timer 1 */

#define SYS_TIMER_CLEAR AMBA_TIMER_T1CLEAR
#define SYS_TIMER_CTRL  AMBA_TIMER_T1CTRL
#define SYS_TIMER_LOAD  AMBA_TIMER_T1LOAD
#define SYS_TIMER_VALUE AMBA_TIMER_T1VALUE

/* Aux Clk is timer 2 */

#define AUX_TIMER_CLEAR AMBA_TIMER_T2CLEAR
#define AUX_TIMER_CTRL  AMBA_TIMER_T2CTRL
#define AUX_TIMER_LOAD  AMBA_TIMER_T2LOAD
#define AUX_TIMER_VALUE AMBA_TIMER_T2VALUE


/*
 * Clock rates depend upon CPU power and work load of application.
 * The values below are minimum and maximum allowed by the hardware.
 * So:
 * min frequency = roundup(clock_rate/(max_counter_value))
 * max frequency = rounddown(clock_rate/(min_counter_value))
 * i.e. SYS_CLK_RATE_MAX = SYS_TIMER_CLK
 *      AUX_CLK_RATE_MAX = AUX_TIMER_CLK
 *
 * However, we must set maxima that are sustainable on a running
 * system determined by experimentation.
 *
 * The 720T values have been determined by experimentation, the others
 * need to be checked.
 */

#define SYS_CLK_RATE_MIN ((SYS_TIMER_CLK+0xFFFF)/0x10000)
#if defined(CPU_720T) || defined(CPU_720T_T)
#define SYS_CLK_RATE_MAX 25000
#elif defined(CPU_740T) || defined(CPU_740T_T)
#define SYS_CLK_RATE_MAX 25000
#elif defined(CPU_920T) || defined(CPU_920T_T)
#define SYS_CLK_RATE_MAX 25000
#elif defined(CPU_940T) || defined(CPU_940T_T)
#define SYS_CLK_RATE_MAX 25000
#elif defined(CPU_946ES) || defined(CPU_946ES_T)
#define SYS_CLK_RATE_MAX 25000
#elif defined(CPU_966ES) || defined(CPU_966ES_T)
#define SYS_CLK_RATE_MAX 6000
#else
#define SYS_CLK_RATE_MAX 9000
#endif

#define AUX_CLK_RATE_MIN ((AUX_TIMER_CLK+0xFFFF)/0x10000)
#if defined(CPU_720T) || defined(CPU_720T_T)
#define AUX_CLK_RATE_MAX 25000
#elif defined(CPU_740T) || defined(CPU_740T_T)
#define AUX_CLK_RATE_MAX 25000
#elif defined(CPU_920T) || defined(CPU_920T_T)
#define AUX_CLK_RATE_MAX 25000
#elif defined(CPU_940T) || defined(CPU_940T_T)
#define AUX_CLK_RATE_MAX 25000
#elif defined(CPU_946ES) || defined(CPU_946ES_T)
#define AUX_CLK_RATE_MAX 25000
#elif defined(CPU_966ES) || defined(CPU_966ES_T)
#define AUX_CLK_RATE_MAX 6000
#else
#define AUX_CLK_RATE_MAX 9000
#endif


/* PCI definitions */

/* Interrupt number for PCI */

#define INT_NUM_IRQ0	INT_LVL_PCI_0

/* Bit field definitions */

#define BIT0                            0x00000001
#define BIT1                            0x00000002
#define BIT2                            0x00000004
#define BIT3                            0x00000008
#define BIT4                            0x00000010
#define BIT5                            0x00000020
#define BIT6                            0x00000040
#define BIT7                            0x00000080
#define BIT8                            0x00000100
#define BIT9                            0x00000200
#define BIT10                           0x00000400
#define BIT11                           0x00000800
#define BIT12                           0x00001000
#define BIT13                           0x00002000
#define BIT14                           0x00004000
#define BIT15                           0x00008000
#define BIT16                           0x00010000
#define BIT17                           0x00020000
#define BIT18                           0x00040000
#define BIT19                           0x00080000
#define BIT20                           0x00100000

/* Handy sizes */

#define SZ_1K                           0x00000400
#define SZ_4K                           0x00001000
#define SZ_8K                           0x00002000
#define SZ_16K                          0x00004000
#define SZ_64K                          0x00010000
#define SZ_128K                         0x00020000
#define SZ_256K                         0x00040000
#define SZ_512K                         0x00080000

#define SZ_1M                           0x00100000
#define SZ_2M                           0x00200000
#define SZ_4M                           0x00400000
#define SZ_8M                           0x00800000
#define SZ_16M                          0x01000000
#define SZ_32M                          0x02000000
#define SZ_64M                          0x04000000
#define SZ_128M                         0x08000000
#define SZ_256M                         0x10000000
#define SZ_512M                         0x20000000

#define SZ_1G                           0x40000000
#define SZ_2G                           0x80000000


/* defines for generic pciIoMapLib.c code */

#define PCI_IN_BYTE(x)		*(volatile UINT8 *) (x)
#define PCI_OUT_BYTE(x,y)	*(volatile UINT8 *) (x) = (UINT8)  y
#define PCI_IN_WORD(x)		*(volatile UINT16 *)(x)
#define PCI_OUT_WORD(x,y)	*(volatile UINT16 *)(x) = (UINT16) y
#define PCI_IN_LONG(x)		*(volatile UINT32 *)(x)
#define PCI_OUT_LONG(x,y)	*(volatile UINT32 *)(x) = (UINT32) y

/* restrict use to the first bus, by default */

#define PCI_MAX_BUS 1

/* memory map as seen by the CPU on the local bus */

#define CPU_PCI_IO_ADRS		0x60000000 	/* PCI I/O space base */
#define CPU_PCI_IO_SIZE		0x10000

#define CPU_PCI_CNFG_ADRS	0x61000000	/* PCI config space */
#define CPU_PCI_CNFG_SIZE	0x1000000

#define CPU_PCI_MEM_ADRS	0x40000000
#define CPU_PCI_MEM_SIZE	0x10000000

/* PCI view of PCI space for PCI devices */

#define PCI_IO_ADRS             0x00000000      /* base of PCI I/O address */
#define PCI2DRAM_BASE_ADRS      0x80000000      /* memory seen from PCI bus */

/* PCI view of PCI memory space for PCI memory devices */

#define PCI_MEM_ADRS		0x40000000	/* base of PCI memory space */

/* PCI address to CPU address offset */

#define PCI2CPU_IO_OFFSET	(CPU_PCI_IO_ADRS - PCI_IO_ADRS)
#define PCI2CPU_MEM_OFFSET	(CPU_PCI_MEM_ADRS - PCI_MEM_ADRS)

/* PCI bus resources */

#define PCI_IO_SIZE		0x00004000	/* PCI I/O slot size */
#define PCI_MEM_SIZE		0x00004000	/* PCI memory slot size */

#define PCI_MEM_ADR0            PCI_MEM_ADRS
#define PCI_IO_ADR0             PCI_IO_ADRS     /* I/O base for CSR 32Bytes */
#define PCI_IO_SIZE0            PCI_IO_SIZE     /* I/O size for CSR */
#define PCI_INT_LVL0            INT_LVL_PCI_0	/* Interrupt level */
#define PCI_INT_VEC0            INT_VEC_PCI_0	/* Interrupt vector */

#define PCI_MEM_ADR1            PCI_MEM_ADR0 + PCI_MEM_SIZE
#define PCI_IO_ADR1             PCI_IO_ADR0 + PCI_IO_SIZE
#define PCI_IO_SIZE1            PCI_IO_SIZE
#define PCI_INT_LVL1            INT_LVL_PCI_1
#define PCI_INT_VEC1            INT_VEC_PCI_1

#define PCI_MEM_ADR2            PCI_MEM_ADR1 + PCI_MEM_SIZE
#define PCI_IO_ADR2             PCI_IO_ADR1 + PCI_IO_SIZE
#define PCI_IO_SIZE2            PCI_IO_SIZE
#define PCI_INT_LVL2            INT_LVL_PCI_2
#define PCI_INT_VEC2            INT_VEC_PCI_2


/* PCI memory base address register configuration mode */

#define FORCE		0x00	/* overwrite membase address register */
#define AUTO		0x01	/* read membase address register */

/*
 * Need to use automatic configuration mode using the resource assigning in
 * pciAssignResources().
 */

#define PCI_REG_MOD	AUTO	/* define the register configuration mode */

#define TYPE_ALLOC	1000


/* Definitions for LED controller and sysLedsReadWrite */

#define LED_BASE        0x1A000000
#define LED_ALPHA 	(LED_BASE + 0x00)
#define LED_LIGHTS	(LED_BASE + 0x04)
#define LED_SWITCHES	(LED_BASE + 0x08)

#define LED_STATUS	0x01

#define LED_0		0x01
#define LED_1		0x02
#define LED_2		0x04
#define LED_4		0x08

#define LED_LEDS_MASK	0x0F


#define ARM966_I_SRAM_ENABLE    (1<<12)
#define ARM966_WBUFF_ENABLE     (1<<3)
#define ARM966_D_SRAM_ENABLE    (1<<2)

#ifdef __cplusplus
}
#endif

#endif	/* INCtemplateh */