configtimer01.c

ti-Chipcon CC1010 1G以下Soc源码库。包括rf,powermodes,clockmodes,flashRW,interrupts,timer,pwm,uart...所有底层驱动源码

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 *      ***   +++   ***                                                      *
 *      ***   + +   ***                                                      *
 *      ***   +                            CHIPCON CC1010                    *
 *      ***   + +   ***                 HAL - ConfigTimer01                  *
 *      ***   +++   ***                                                      *
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 * Author:              ROH                                                  *
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 * Revision history:                                                         *
 *                                                                           *
 * $Log: ConfigTimer01.c,v $
 * Revision 1.1  2002/10/14 13:04:30  tos
 * Initial version in CVS.
 *
 *                                                                           *
 ****************************************************************************/

#include <chipcon/hal.h>

//----------------------------------------------------------------------------
// ulong halConfigTimer01(...);
//
//  Description:
//      This function configures timer 0 or 1 (depending on the value given in
//      _option_ as either an interrupt timer (an interrupt is generated at
//      certain intervals in time, as specified by _period) or an interrupt
//      pulse counter (an interrupt when _period_ number of pulses have
//      been detected on P3.4/P3.5 for timer0/timer1.) 
//      Some timer settings (with long timeouts) require that the user 
//      initializes timer register in the interrupt service routine (ISR.) This
//      should be done by using the appropriate version of the 
//      ISR_TIMERx_ADJUST(m) macro with the word pointed to by _modulo_ as an
//      argument. The _modulo_ argument takes a pointer to a word, if it is 
//      NULL, many timer settings will be unavailable. It is the responsibility
//      of the programmer to make sure that the appropriate timer ISR has been
//      declared (and that it begins with the obligatory ISR_TIMERx_ADJUST(m) 
//      macro). The timer must be started with macro TIMERx_RUN(TRUE).
//
//  Arguments:
//      byte options
//          Options indicating which timer to configure and how. Different
//          constants for _option_ is defined below.
//      ulong period
//          The desired period between interrupts in microseconds in timer
//          mode, or the number of counted pulses between interrupts in counter
//          mode.
//      word clkFreq
//          The XOSC clock frequency in kHz.
//      word xdata* modulo
//          A pointer to a word (in xdata) which after the function has returned
//          contains the value to supply to the obligatory macro invocation of
//          ISR_TIMERx_ADJUST(m) at the start of the timer ISR.
//
//  Return value:
//      ulong
//          In timer mode, the actual period in microseconds between interrupts
//          or zero if the period is impossible to achieve.
//          In counter mode, zero if the supplied count value is impossible to
//          achieve, otherwise one.
//----------------------------------------------------------------------------
ulong halConfigTimer01(byte options, ulong period, word clkFreq, word* modulo) {
    byte ckcon, tmod, thx, tlx;
    
    if (modulo) 
        *modulo=0;
    else
        return 0;
    if (options&TIMER01_INT_PULSE_COUNTER) {
        // Pulse counter
        if (!(period&0xFFFFFF00)) {   // <256
            tmod=0x06;      // Mode 2 (8-bit auto-reload) + clocked by T0/T1
            thx=tlx=0-(byte)period;
        } else {
            tmod=0x05;      // Mode 1 (16-bit) + clocked by T0/T1
            *modulo=0-(word)period;
            thx=*modulo>>8; tlx=*modulo&0xFF;
        }

        // Setup hardware registers
        if (options&TIMER1) {
            TMOD=(TMOD&0x0F)|(tmod<<4);
            TH1=thx; TL1=tlx;
        } else {
            TMOD=(TMOD&0xF0)|tmod;
            TH0=thx; TL0=tlx;
        }
        return 1;
    } else {
        // Timer
        period=period*clkFreq/4000;
        if (period&0xFFFF0000) {   // >65535
            // Using CLK/12
            ckcon=0;
            if ((period/=3)&0xFFFF0000)     // >65535
                return 0;            
        } else {
            // Using CLK/4                
            ckcon=1;
        }
        
        // Choose mode
        if (!(period&0xFFFFFF00)) {   // <256
            tmod=0x02;      // Mode 2 (8-bit auto-reload) + clocked by CLK/4 or CLK/12
            thx=tlx=0-(byte)period;
        } else {
            tmod=0x01;      // Mode 1 (16-bit) + clocked by CLK/4 or CLK/12
            *modulo=0-(word)period;
            thx=*modulo>>8; tlx=*modulo&0xFF;
        }
        
        // Setup hardware registers
        if (options&TIMER1) {
            TMOD=(TMOD&0x0F)|(tmod<<4);
            TH1=thx; TL1=tlx;
            CKCON=(CKCON&~0x10) | ((ckcon&1)<<4);
            if (!(options&TIMER01_NO_INT_TIMER)) {
                TR1=0;
                TF1=0;
                ET1=1;
                EA=1;
            }                
        } else {
            TMOD=(TMOD&0xF0)|tmod;
            TH0=thx; TL0=tlx;
            CKCON=(CKCON&~0x0F) | ((ckcon&1)<<3);
            if (!(options&TIMER01_NO_INT_TIMER)) {
                TR0=0;
                TF0=0;
                ET0=1;
                EA=1;
            }
        }
        
        // Return actual period
        period*=(ckcon) ? 4000 : 12000;
        period/=clkFreq;
        
        return period;
    }    
}