5502_zbtram.c

外设存储器接口程序

/******************************************************************************/
/*  Copyright 2004 by SEED Electronic Technology LTD.                         */
/*  All rights reserved. SEED Electronic Technology LTD.                      */
/*  Restricted rights to use, duplicate or disclose this code are             */
/*  granted through contract.                                                 */
/*                                                                            */
/*                                                                            */
/******************************************************************************/
/*----------------------------------------------------------------------------*/
/* MODULE NAME... ZBTRAM											  		  */
/* FILENAME...... 5502_ZBTRAM.c												  */
/* ChIP TYPE......cy7c1354b							                          */											  
/* DATE CREATED.. 6/24/2004 											  	  */
/* PROJECT....... write and read operation on ZBTRAM of DEC_5502			  */
/* COMPONENT..... 															  */
/* PREREQUISITS.. 															  */
/*----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------*/
/* DESCRIPTION:  															  */
/*   																		  */
/* This is an example of write and read ZBTRAM of DEC5502					  */
/*----------------------------------------------------------------------------*/
#include <csl.h>
#include <csl_pll.h>
#include <csl_emif.h>
#include <csl_chip.h>
#include <stdio.h>

#define DataLength 1024

/*定义宏来操作系统控制寄存器2*/
#define SYSCNTL2 (*(volatile unsigned int *)(0x280001)) 

Uint32	SourData[DataLength];
#pragma DATA_SECTION (SourData,".sourdata")		// Located in ZBTRAM sector                 


/*ZBTRAM的EMIF设置*/
EMIF_Config MyEmifConfig = {
EMIF_GBLCTL1_RMK(					// EMIF Global Control Register 1
  EMIF_GBLCTL1_NOHOLD_HOLD_ENABLED,	// Hold enable
  EMIF_GBLCTL2_EK2HZ_HIGHZ,			// EMIF_GBLCTL1_EK1HZ_EK1ENHigh-Z control
  EMIF_GBLCTL1_EK1EN_ENABLED		// ECLKOUT1 Enable
  ),
EMIF_GBLCTL2_RMK(					// EMIF Global Control Register 2
  EMIF_GBLCTL2_EK2RATE_1XCLK,		// ECLKOUT2 Rate
  EMIF_GBLCTL2_EK2HZ_HIGHZ,			// EMIF_GBLCTL2_EK2HZ_EK2ENEK2HZ = 0, ECLKOUT2 is driven with value specified by EKnEN during
  EMIF_GBLCTL2_EK2EN_ENABLED		// ECLKOUT2 Enable (enabled by default)
  ), 
EMIF_CE1CTL1_RMK(					// CE1 Space Control Register 1
  EMIF_CE1CTL1_TA_OF(3),			// Turn-Around time
  EMIF_CE1CTL1_READ_STROBE_OF(63),	// Read strobe width
  EMIF_CE1CTL1_MTYPE_16BIT_ASYNC,	// Access type
  EMIF_CE1CTL1_WRITE_HOLD_MSB_HIGH,	// Write hold width MSB bit
  EMIF_CE1CTL1_READ_HOLD_OF(7)		// Read hold width
  ),
EMIF_CE1CTL2_RMK(					// CE1 Space Control Register 2
  EMIF_CE1CTL2_WRITE_SETUP_OF(15),	// Write setup width
  EMIF_CE1CTL2_WRITE_STROBE_OF(63),	// Write strobe width
  EMIF_CE1CTL2_WRITE_HOLD_OF(3),	// Write hold width
  EMIF_CE1CTL2_READ_SETUP_OF(15)	// Read setup width
  ),
EMIF_CE0CTL1_RMK(					// CE0 Space Control Register 1
  EMIF_CE0CTL1_TA_DEFAULT,
  EMIF_CE0CTL1_READ_STROBE_DEFAULT,
  EMIF_CE0CTL1_MTYPE_32BIT_SBSRAM,
  EMIF_CE0CTL1_WRITE_HOLD_MSB_DEFAULT,
  EMIF_CE0CTL1_READ_HOLD_DEFAULT
  ),
EMIF_CE0CTL2_RMK(					// CE0 Space Control Register 2
  EMIF_CE0CTL2_WRITE_SETUP_DEFAULT,
  EMIF_CE0CTL2_WRITE_STROBE_DEFAULT,
  EMIF_CE0CTL2_WRITE_HOLD_DEFAULT,
  EMIF_CE0CTL2_READ_SETUP_DEFAULT
  ),
EMIF_CE2CTL1_RMK(					// CE2 Space Control Register 1
  EMIF_CE2CTL1_TA_DEFAULT,			// Not use for SDRAM (asynchronous memory types only)
  EMIF_CE2CTL1_READ_STROBE_DEFAULT,	// Read strobe width
  EMIF_CE2CTL1_MTYPE_32BIT_SDRAM,	// 32-bit-wide SDRAM
  EMIF_CE2CTL1_WRITE_HOLD_DEFAULT,	// Write hold width
  EMIF_CE2CTL1_READ_HOLD_DEFAULT	// Read hold width
  ),
EMIF_CE2CTL2_RMK(					// CE2 Space Control Register 2
  EMIF_CE2CTL2_WRITE_SETUP_DEFAULT,	// Write setup width
  EMIF_CE2CTL2_WRITE_STROBE_DEFAULT,// Write strobe width
  EMIF_CE2CTL2_WRITE_HOLD_DEFAULT,	// Write hold width
  EMIF_CE2CTL2_READ_SETUP_DEFAULT	// Read setup width
  ),
EMIF_CE3CTL1_RMK(					// CE3 Space Control Register 1
  EMIF_CE3CTL1_TA_DEFAULT,			// Not use for SDRAM (asynchronous memory types only)
  EMIF_CE3CTL1_READ_STROBE_DEFAULT,	// Read strobe width
  EMIF_CE2CTL1_MTYPE_32BIT_SDRAM,	// 32-bit-wide SDRAM
  EMIF_CE3CTL1_WRITE_HOLD_DEFAULT,	// Write hold width
  EMIF_CE3CTL1_READ_HOLD_DEFAULT	// Read hold width
  ),
EMIF_CE3CTL2_RMK(					// CE3 Space Control Register 2
  EMIF_CE3CTL2_WRITE_SETUP_DEFAULT,	// Write setup width
  EMIF_CE3CTL2_WRITE_STROBE_DEFAULT,// Write strobe width
  EMIF_CE3CTL2_WRITE_HOLD_DEFAULT,	// Write hold width
  EMIF_CE3CTL2_READ_SETUP_DEFAULT	// Read setup width
  ),
EMIF_SDCTL1_RMK(					// SDRAM Control Register 1
  EMIF_SDCTL1_TRC_OF(6),			// Specifies tRC value of the SDRAM in EMIF clock cycles.
  EMIF_SDCTL1_SLFRFR_DISABLED		// Auto-refresh mode
  ),
EMIF_SDCTL2_RMK(					// SDRAM Control Register 2
  0x11,								// 4 banks,11 row address, 8 column address
  EMIF_SDCTL2_RFEN_ENABLED,			// Refresh enabled
  EMIF_SDCTL2_INIT_INIT_SDRAM,
  EMIF_SDCTL2_TRCD_OF(1),			// Specifies tRCD value of the SDRAM in EMIF clock cycles
  EMIF_SDCTL2_TRP_OF(1)				// Specifies tRP value of the SDRAM in EMIF clock cycles
  ),
0x61B,								// SDRAM Refresh Control Register 1
0x0300,								// SDRAM Refresh Control Register 2
EMIF_SDEXT1_RMK(					// SDRAM Extension Register 1
  EMIF_SDEXT1_R2WDQM_1CYCLE,
  EMIF_SDEXT1_RD2WR_3CYCLES,
  EMIF_SDEXT1_RD2DEAC_1CYCLE,
  EMIF_SDEXT1_RD2RD_1CYCLE,
  EMIF_SDEXT1_THZP_OF(1),			// tPROZ2=2
  EMIF_SDEXT1_TWR_OF(0),			//
  EMIF_SDEXT1_TRRD_2CYCLES,
  EMIF_SDEXT1_TRAS_OF(4),
  EMIF_SDEXT1_TCL_2CYCLES
  ),
EMIF_SDEXT2_RMK(					// SDRAM Extension Register 2
  EMIF_SDEXT2_WR2RD_0CYCLES,
  EMIF_SDEXT2_WR2DEAC_1CYCLE,
  0,
  EMIF_SDEXT2_R2WDQM_1CYCLE
  ),
EMIF_CE1SEC1_DEFAULT,				// CE1 Secondary Control Register 1
EMIF_CE0SEC1_RMK(					// CE0 Secondary Control Register 1
  EMIF_CE0SEC1_SNCCLK_SYNC_ECLKOUT2,
  EMIF_CE0SEC1_REN_ADS,                   
  EMIF_CE0SEC1_CEEXT_CE_TIED_TO_SNCCRL, 
  EMIF_CE0SEC1_SYNCWL_2CYCLES,
  EMIF_CE0SEC1_SYNCRL_2CYCLES),			
EMIF_CE2SEC1_DEFAULT,				// CE2 Secondary Control Register 1
EMIF_CE3SEC1_DEFAULT,				// CE3 Secondary Control Register 1
EMIF_CESCR_DEFAULT					// CE Size Control Register								
  };

main()
{
    Uint16 i;
    Uint16 Errcount = 0;
    
	/*初始化CSL库*/	
    CSL_init();
    
    /*设置系统的运行速度为300MHz*/
    PLL_setFreq(1, 0xF, 0, 1, 3, 3, 0);
    
    /*EMIF为全EMIF接口*/
    CHIP_RSET(XBSR,0x0001);
    
    /*初始化DSP的EMIF接口*/
    EMIF_config(&MyEmifConfig); 
    
    SYSCNTL2 = 0x20;		// 使能ZBTRAM
    for(i=0; i<200; i++)
    {}
    
    /* 写ZBTRAM */
    for(i=0;i<DataLength;i++)
    {
      	SourData[i] = i;
    }
    
    Errcount = 0;
    /* 读ZBTRAM并校验是否正确 */
   	for(i=0;i<DataLength;i++)
   	{
     	if(i != SourData[i])
     	Errcount++;
   	} 
   	
    if(Errcount != 0)
    printf("SEED_DEC5502 ZBTRAM 操作失败\n");
    else
    printf("SEED_DEC5502 ZBTRAM 操作成功\n");
}

/******************************************************************************\
* End of 5502_ZBTRAM.c
\******************************************************************************/