dec5502_flashboot.c

DSPBOOTLOADER程序

/******************************************************************************/
/*  Copyright 2004 by SEED Electronic Technology LTD.                         */
/*  All rights reserved. SEED Electronic Technology LTD.                      */
/*  Restricted rights to use, duplicate or disclose this code are             */
/*  granted through contract.                                                 */
/*                                                                            */
/*                                                                            */
/******************************************************************************/
/*----------------------------------------------------------------------------*/
/* MODULE NAME... Dec5502_flash											 	  */
/* FILENAME...... DEC5502_FLASHBOOT.c										  */
/* DATE CREATED.. Wed 7/20/2004 											  */
/* PROJECT....... Flash boot operation							  			  */
/* COMPONENT..... 															  */
/* PREREQUISITS.. 															  */
/*----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------*/
/* DESCRIPTION:  															  */
/*   																		  */
/* This is an example of flash boot program				  					  */
/*----------------------------------------------------------------------------*/
#include <csl.h>
#include <csl_pll.h>
#include <csl_emif.h>
#include <csl_chip.h>
#include "SST39VF400A.h"


/* Define FLASH write variable */
unsigned int *  Boot_Start;
unsigned int Low_Word;
unsigned int High_Word;
unsigned int Section_count;
unsigned int * Section_add;
unsigned long int i;

/* Entry point address,register configuration count,section parameter */
#define Entry_Point 	0x000017C4		// 定义32位进入点地址

#define REG_COFIG_COUNT	0x00000001		// 配置寄存器配置计数器
#define DELAY_CONFIG	0xFFFFFFF0		// 延时0xFFF0

#define BIGSECT_COUNT	0x000008E0
#define BIGSECT_ADDRESS	0x00001000

/*FLASH的EMIF设置*/
EMIF_Config MyEmifConfig = {
EMIF_GBLCTL1_RMK(					// EMIF Global Control Register 1
  EMIF_GBLCTL1_NOHOLD_HOLD_ENABLED,	// Hold enable
  EMIF_GBLCTL1_EK1HZ_HIGHZ,			// EMIF_GBLCTL1_EK1HZ_EK1ENHigh-Z control
  EMIF_GBLCTL1_EK1EN_ENABLED		// ECLKOUT1 Enable
  ),
EMIF_GBLCTL2_RMK(					// EMIF Global Control Register 2
  EMIF_GBLCTL2_EK2RATE_1XCLK,		// ECLKOUT2 Rate
  EMIF_GBLCTL2_EK2HZ_HIGHZ,			// EMIF_GBLCTL2_EK2HZ_EK2ENEK2HZ = 0, ECLKOUT2 is driven with value specified by EKnEN during
  EMIF_GBLCTL2_EK2EN_DISABLED		// ECLKOUT2 Enable (enabled by default)
  ), 
EMIF_CE1CTL1_RMK(					// CE1 Space Control Register 1
  EMIF_CE1CTL1_TA_OF(3),			// Turn-Around time
  EMIF_CE1CTL1_READ_STROBE_OF(6),	// Read strobe width
  EMIF_CE1CTL1_MTYPE_16BIT_ASYNC,	// Access type
  EMIF_CE1CTL1_WRITE_HOLD_MSB_LOW,	// Write hold width MSB bitHIGH
  EMIF_CE1CTL1_READ_HOLD_OF(3)		// Read hold width
  ),
EMIF_CE1CTL2_RMK(					// CE1 Space Control Register 2
  EMIF_CE1CTL2_WRITE_SETUP_OF(4),	// Write setup width
  EMIF_CE1CTL2_WRITE_STROBE_OF(10),	// Write strobe width
  EMIF_CE1CTL2_WRITE_HOLD_OF(2),	// Write hold width
  EMIF_CE1CTL2_READ_SETUP_OF(2)		// Read setup width
  ),
EMIF_CE0CTL1_RMK(					// CE0 Space Control Register 1
  EMIF_CE0CTL1_TA_DEFAULT,
  EMIF_CE0CTL1_READ_STROBE_DEFAULT,
  EMIF_CE0CTL1_MTYPE_DEFAULT,
  EMIF_CE0CTL1_WRITE_HOLD_MSB_DEFAULT,
  EMIF_CE0CTL1_READ_HOLD_DEFAULT
  ),
EMIF_CE0CTL2_RMK(					// CE0 Space Control Register 2
  EMIF_CE0CTL2_WRITE_SETUP_DEFAULT,
  EMIF_CE0CTL2_WRITE_STROBE_DEFAULT,
  EMIF_CE0CTL2_WRITE_HOLD_DEFAULT,
  EMIF_CE0CTL2_READ_SETUP_DEFAULT
  ),
EMIF_CE2CTL1_RMK(					// CE2 Space Control Register 1
  EMIF_CE2CTL1_TA_DEFAULT,			// Not use for SDRAM (asynchronous memory types only)
  EMIF_CE2CTL1_READ_STROBE_DEFAULT,	// Read strobe width
  EMIF_CE2CTL1_MTYPE_32BIT_SDRAM,	// 32-bit-wide SDRAM
  EMIF_CE2CTL1_WRITE_HOLD_DEFAULT,	// Write hold width
  EMIF_CE2CTL1_READ_HOLD_DEFAULT	// Read hold width
  ),
EMIF_CE2CTL2_RMK(					// CE2 Space Control Register 2
  EMIF_CE2CTL2_WRITE_SETUP_DEFAULT,	// Write setup width
  EMIF_CE2CTL2_WRITE_STROBE_DEFAULT,// Write strobe width
  EMIF_CE2CTL2_WRITE_HOLD_DEFAULT,	// Write hold width
  EMIF_CE2CTL2_READ_SETUP_DEFAULT	// Read setup width
  ),
EMIF_CE3CTL1_RMK(					// CE3 Space Control Register 1
  EMIF_CE3CTL1_TA_DEFAULT,			// Not use for SDRAM (asynchronous memory types only)
  EMIF_CE3CTL1_READ_STROBE_DEFAULT,	// Read strobe width
  EMIF_CE2CTL1_MTYPE_32BIT_SDRAM,	// 32-bit-wide SDRAM
  EMIF_CE3CTL1_WRITE_HOLD_DEFAULT,	// Write hold width
  EMIF_CE3CTL1_READ_HOLD_DEFAULT	// Read hold width
  ),
EMIF_CE3CTL2_RMK(					// CE3 Space Control Register 2
  EMIF_CE3CTL2_WRITE_SETUP_DEFAULT,	// Write setup width
  EMIF_CE3CTL2_WRITE_STROBE_DEFAULT,// Write strobe width
  EMIF_CE3CTL2_WRITE_HOLD_DEFAULT,	// Write hold width
  EMIF_CE3CTL2_READ_SETUP_DEFAULT	// Read setup width
  ),
EMIF_SDCTL1_RMK(					// SDRAM Control Register 1
  EMIF_SDCTL1_TRC_OF(6),			// Specifies tRC value of the SDRAM in EMIF clock cycles.
  EMIF_SDCTL1_SLFRFR_DISABLED		// Auto-refresh mode
  ),
EMIF_SDCTL2_RMK(					// SDRAM Control Register 2
  0x11,								// 4 banks,11 row address, 8 column address
  EMIF_SDCTL2_RFEN_ENABLED,			// Refresh enabled
  EMIF_SDCTL2_INIT_INIT_SDRAM,
  EMIF_SDCTL2_TRCD_OF(1),			// Specifies tRCD value of the SDRAM in EMIF clock cycles
  EMIF_SDCTL2_TRP_OF(1)				// Specifies tRP value of the SDRAM in EMIF clock cycles
  ),
0x61B,								// SDRAM Refresh Control Register 1
0x0300,								// SDRAM Refresh Control Register 2
EMIF_SDEXT1_RMK(					// SDRAM Extension Register 1
  EMIF_SDEXT1_R2WDQM_1CYCLE,
  EMIF_SDEXT1_RD2WR_3CYCLES,
  EMIF_SDEXT1_RD2DEAC_1CYCLE,
  EMIF_SDEXT1_RD2RD_1CYCLE,
  EMIF_SDEXT1_THZP_OF(1),			// tPROZ2=2
  EMIF_SDEXT1_TWR_OF(0),			//
  EMIF_SDEXT1_TRRD_2CYCLES,
  EMIF_SDEXT1_TRAS_OF(4),
  EMIF_SDEXT1_TCL_2CYCLES
  ),
EMIF_SDEXT2_RMK(					// SDRAM Extension Register 2
  EMIF_SDEXT2_WR2RD_0CYCLES,
  EMIF_SDEXT2_WR2DEAC_1CYCLE,
  0,
  EMIF_SDEXT2_R2WDQM_1CYCLE
  ),
EMIF_CE1SEC1_DEFAULT,				// CE1 Secondary Control Register 1
EMIF_CE0SEC1_DEFAULT,				// CE0 Secondary Control Register 1
EMIF_CE2SEC1_DEFAULT,				// CE2 Secondary Control Register 1
EMIF_CE3SEC1_DEFAULT,				// CE3 Secondary Control Register 1
EMIF_CESCR_DEFAULT					// CE Size Control Register								
  };
  
main()
{
	/*初始化CSL库*/	
    CSL_init();
    
    /*设置系统的运行速度为300MHz*/
    PLL_setFreq(1, 0xF, 0, 1, 3, 3, 0);
	
	/*EMIF为全EMIF接口*/
    CHIP_RSET(XBSR,0x0001);
    
  	/*初始化DSP的外部EMIF*/
    EMIF_config(&MyEmifConfig);
    
    /*Boot table start address definition*/
	Boot_Start =(unsigned int *)0x200000;
	
    /*Erase a block of flash for boot table programming*/
    Erase_One_Block (Boot_Start);
    
    /*************** 写32位进入点地址 ***************************/
     
    High_Word = (Entry_Point & 0xFFFF0000)>>16;
    Program_One_Word (High_Word, Boot_Start++);
    Low_Word = Entry_Point & 0x0000FFFF;
    Program_One_Word (Low_Word, Boot_Start++);
   
    
    /*************** 写32位寄存器配置计数器 **********************/
   
    High_Word = (REG_COFIG_COUNT & 0xFFFF0000)>>16;
    Program_One_Word (High_Word, Boot_Start++);
    Low_Word = REG_COFIG_COUNT & 0x0000FFFF;
    Program_One_Word (Low_Word, Boot_Start++);
    
     /*************** 写32位延时寄存器 **********************/
   
    High_Word = (DELAY_CONFIG & 0xFFFF0000)>>16;
    Program_One_Word (High_Word, Boot_Start++);
    Low_Word = DELAY_CONFIG & 0x0000FFFF;
    Program_One_Word (Low_Word, Boot_Start++);
    
   	/*************** 写程序段 ***********************************/
   	/* Configure section byte count */
   
   	
   	High_Word = (BIGSECT_COUNT & 0xFFFF0000)>>16;
   	Program_One_Word (High_Word, Boot_Start++);	
   	Low_Word = BIGSECT_COUNT & 0x0000FFFF;
   	Program_One_Word (Low_Word, Boot_Start++);
   	
   	/* Configure section start address */
   
   	
   	High_Word = (BIGSECT_ADDRESS & 0xFFFF0000)>>16;
   	Program_One_Word (High_Word, Boot_Start++);	
   	Low_Word = BIGSECT_ADDRESS & 0x0000FFFF;
   	Program_One_Word (Low_Word, Boot_Start++);
   	
   	/* Copy data to this section */
   	Section_count = BIGSECT_COUNT>>1;
   	Section_add = (unsigned int *)(BIGSECT_ADDRESS>>1);
   	for(i=0; i<Section_count; i++)
   	{
   		Program_One_Word (*Section_add++, Boot_Start++);
   	}		
   	
   	/* Write 32-bit zero byte count to end the boot table */
   	Program_One_Word (0x0000, Boot_Start++);
   	Program_One_Word (0x0000, Boot_Start); 

}

/******************************************************************************\
* End of DEC5502_FLSHBOOT.c
\******************************************************************************/