617.txt

用于简单电子时钟的设计的VRRILOG代码

module dk(clk,F1,out,led);
output [7:0]led;
output [7:0]out;
output F1;
input clk; 
reg [7:0] led;  //数字显示位置
reg [7:0] out;  // 输出数字
reg [7:0] out1; //保存时钟的8个数字
reg [7:0] out2;
reg [7:0] out3;
reg [7:0] out4;
reg [7:0] out5;
reg [7:0] out7;
reg [7:0] out8;
reg F1;
reg [2:0]in2; // 第2位显 0~5
reg [3:0]in4; // 第4位显 0~9
reg [2:0]in5; // 第5位显 0~5
reg [3:0]in7; // 第7位显 0~9
reg [1:0]in8; // 第8位显 1~2、不显示
reg [2:0]a;  // 显示管全显控制位
integer j;
integer t;
always @(posedge clk)
begin
if(j==9999999)
              begin
		j<=0;
		F1<=~F1;
	     end
 else 
    j<=j+1;
end
initial t<=0;
always @(posedge F1)
begin
	// 用于记忆显示数字
  case(a) // 从第8位~第一位
      3'd0:  //1
	begin
	case(t)
        3'd0: out1 <= 8'b00111111;
		3'd1: out1 <= 8'b00110000;
		3'd2: out1 <= 8'b01011011;
		3'd3: out1<= 8'b01001111;
		3'd4: out1<= 8'b01100110;
		3'd5: out1 <= 8'b01101101;
        3'd6: out1 <= 8'b01111101;
		3'd7: out1 <= 8'b00100111;
		3'd8: out1 <= 8'b01111111;
		3'd9: out1 <= 8'b01101111;
        default  
		begin
			out1 <= 8'b00111111;	// 显示0		
			t<= 0;     // 重新赋为0，加1为1
			in2<=in2 + 3'b001; // 高一位加一
		end
		         endcase
            t<= t+1;
	end
	3'd1: //2
	begin 
		case(in2)  // 使用default来使高一位加一
		3'd0: out1 <= 8'b00111111;
		3'd1: out1 <= 8'b00110000;
		3'd2: out1 <= 8'b01011011;
		3'd3: out1<= 8'b01001111;
		3'd4: out1<= 8'b01100110;
		3'd5: out1 <= 8'b01101101;
		default:
		begin
			out2 <= 8'b00111111;	// 显示0		
			in2 <= 3'b000;     // 重新赋为0
			in4 <= in4 + 4'b0001; // 高一位加一
		end
		endcase
	end
	3'd2:  //3
	begin
		out3 <= 8'b01000000; // 显示 -
	end
	3'd3: // 4
	begin
		case(in4)  // 使用default来使高一位加一
		3'd0: out1 <= 8'b00111111;
		3'd1: out1 <= 8'b00110000;
		3'd2: out1 <= 8'b01011011;
		3'd3: out1<= 8'b01001111;
		3'd4: out1<= 8'b01100110;
		3'd5: out1 <= 8'b01101101;
        3'd6: out1 <= 8'b01111101;
		3'd7: out1 <= 8'b00100111;
		3'd8: out1 <= 8'b01111111;
		3'd9: out1 <= 8'b01101111;
		default:
		begin
			out4 <= 8'b00111111;	// 显示0		
			in4 <= 4'b0000;     // 重新赋为0
			in5 <= in5 + 3'b001; // 高一位加一
		end
		endcase 
	end
	3'd4:  //5
	begin
		case(in5)  // 使用default来使高一位加一
		3'd0: out1 <= 8'b00111111;
		3'd1: out1 <= 8'b00110000;
		3'd2: out1 <= 8'b01011011;
		3'd3: out1<= 8'b01001111;
		3'd4: out1<= 8'b01100110;
		3'd5: out1 <= 8'b01101101;
		default:
		begin
			out5 <= 8'b00111111;	// 显示0		
			in5 <= 3'b000;     // 重新赋为0
			in7 <= in7 + 4'b0001; // 高一位加一
		end
		endcase
	end
	3'd5:  //6
	begin
		out3 <= 8'b01000000; // 显示 -
	end
	3'd6:  //7
	begin
		case(in7)
		3'd0: out1 <= 8'b00111111;
		3'd1: out1 <= 8'b00110000;
		3'd2: out1 <= 8'b01011011;
		3'd3: out1<= 8'b01001111;
		4'd4: 						// 显示5; 25:00要变为1:00
		begin 
			if(in8 == 2'b10) // 第8位显示2
			begin
				out7 <=8'b00111111;// 显示1
				in7 <= 4'b0000;     // 重新赋为0,显示为1
				in8 <= 2'b00; // 高一位赋为0,不显示
			end
			else                    
				out7 <= 8'b01100110;  
		end
		3'd5: out1 <= 8'b01101101;
        3'd6: out1 <= 8'b01111101;
		3'd7: out1 <= 8'b00100111;
		3'd8: out1 <= 8'b01111111;
		3'd9: out1 <= 8'b01101111;// 显示9
		4'd9: 
		begin  // 显示0,高位加一
			out7 <= 8'b00111111;  // 显示0
			in8 <= in8 + 2'b01; // 高一位加一
			in7 <= in7 + 4'b0001; // 使不改变高位	
		end
		4'd10: 	out7 <= 8'b00111111;  // 显示0	
		default:
		begin
			out7 <= 8'b00000110;	// 显示1	
			in7 <= 4'b0000;     // 重新赋为0，显示为1
		end
		endcase
	end
	3'd7:  //8
	begin
		case(in8)  
		2'd0: out8 <= 8'b00000000;  // 不显示
		2'd1: out8 <= 8'b00000110;
		2'd2: out8 <= 8'b01011011;
		default:out8 <= 8'b00000000;	// 不显示		
		endcase
	end
	endcase
	a <= a+3'b001;
	
	
	
	//  用于输出到显示管
	a <= a+3'b111;  // mainin-1
	case(a)
	3'd0:
	begin
		out <= out1;
		led <= 8'b11101111;
	end
	3'd1:
	begin
		out <= out2;
		led <= 8'b11110111;	
	end
	3'd2:
	begin
		out <= out3;
		led <= 8'b11111101; 
	end
	3'd3:
	begin
		out <= out4;
		led <= 8'b11111110; 
	end
	3'd4:
	begin
		out <= out5;
		led <= 8'b11111011; 
	end
	3'd5:
	begin
		out <= out3;
		led <= 8'b01111111; 
	end
	3'd6:
	begin
		out <= out7;
		led <= 8'b10111111; 
	end 
	3'd7:
	begin
		out <= out8;
		led <= 8'b11011111; 
	end
	endcase
	a <= a+3'b001;
end
endmodule