📄 mac.c
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/**************************************************************************************************
*
* Copyright (c) 2001 - 2003 Winbond Electronics Corp. All rights reserved.
*
* FILENAME
* mac.c
*
* VERSION
* 1.0
*
* DESCRIPTION
* Main functions of W90N740 MAC Diagnostic Program. This program will receive any packets
* from one Ethernet port, then send the packets through another port. The symbol
* EXTERNAL_LOOPBACK_PORT define the port for sending packets. When running this program,
* please plug a loop-back connector at the Ethernet port (EXTERNAL_LOOPBACK_PORT) and connect
* the other port to a LAN or a test machine for receiving packets.
*
* DATA STRUCTURES
* None
*
* FUNCTIONS
* 1. TimerX_ISR()
* 2. TimerInitialize()
* 3. ShowCurTime()
*
* HISTORY
* 04/14/2003 Ver 1.0 Created by PC30 Jen-Hao Tsai
*
* 04/18/2003 Modified by PC30 Min-Nan Cheng
*
* REMARK
* None
*
*************************************************************************************************/
#include <stdarg.h>
#include <string.h>
#include "740defs.h"
#include "mac.h"
// fixed buffers, just for testing !
#define RxFDBaseAddr0 0x80400000 //descriptor buffer
#define TxFDBaseAddr0 0x80400200
#define RxFBABaseAddr0 0x80400300 //data buffer
#define TxFBABaseAddr0 0x8040c100
#define RxFBALimitAddr0 0x8047fd80
#define RxFDBaseAddr1 0x80480000 //descriptor buffer
#define TxFDBaseAddr1 0x80480200
#define RxFBABaseAddr1 0x80480300 //data buffer
#define TxFBABaseAddr1 0x8048c100
#define RxFBALimitAddr1 0x804ffd80
#define EXTERNAL_LOOPBACK_PORT 1 //can be 0 or 1
#define PHY_Auto_Negotiation //define this symbol for doing PHY auto-negotiation
U32 RxFrameBuffer0 = (U32)TxFBABaseAddr0 ;
U32 RxFrameBuffer1 = (U32)TxFBABaseAddr1 ;
// Global variables used for MAC driver
volatile U32 gMCMDR = MCMDR_RXON | MCMDR_SPCRC | MCMDR_EnMDC | MCMDR_FDUP; // | MCMDR_AEP;
volatile U32 gMIEN = EnTXINTR | EnRXINTR | EnRXGD | EnTXCP |
EnTxBErr | EnRxBErr; // | EnRDU | EnTDU; //| EnALIE; //|EnCRCE ;
//volatile U32 gCAMCMR = CAM_ECMP; //|CAM_AUP;
//Accept ANY kind of packet (Unicast, Broadcasr and Multicase) !!!
volatile U32 gCAMCMR = CAM_ECMP | CAM_AUP | CAM_AMP | CAM_ABP;
volatile U32 gCTxFDPtr[2], gWTxFDPtr[2], gCRxFDPtr[2];
volatile U32 gCam0M_0 = 0 , gCam0L_0 = 0;
volatile U32 gCam0M_1 = 0 , gCam0L_1 = 0;
volatile U8 MyMacSrcAddr[2][6] ;
volatile int gErrorPacketCnt[2] ;
volatile U32 gTxErrPacketCnt[2]; //CMN
volatile U32 gRxErrPacketCnt[2]; //CMN
volatile int MacRxDoneFlagForLoopBackCheck[2] ;
volatile int MacTxDoneFlagForLoopBackCheck[2] ;
// Global variable structure for store status
volatile pMACTxStatus gsMacTxStatus[2];
volatile pMACRxStatus gsMacRxStatus[2];
// for DIAG message
#define TIMER_CHANNEL 1 //Timer channel 1
volatile U32 PreTicks[2];
volatile U32 PreTxBytes[2], PreRxBytes[2];
volatile U32 PktSeq = 0;
volatile U32 TxPktSeq = 0;
volatile U32 RxPktSeq = 0;
volatile U32 TxPktSeqWanted = 0;
volatile U32 RxPktSeqWanted = 0;
volatile U32 TxPktSeqErr = 0;
volatile U32 RxPktSeqErr = 0;
volatile U32 DoChk = 0;
void ShowTxRxStatusWithTime()
{
volatile U32 t_hr, t_min, t_sec;
volatile U32 TxRate[2], RxRate[2];
U32 ticks;
int num;
ticks = cur_ticks; //get current tick count !
for (num=0; num<2; num++)
{
RxRate[num] = ((gsMacRxStatus[num].RxBytes - PreRxBytes[num]) * 100 * 8) / ((ticks - PreTicks[num]) * 1024);
TxRate[num] = ((gsMacTxStatus[num].TxBytes - PreTxBytes[num]) * 100 * 8) / ((ticks - PreTicks[num]) * 1024);
PreTxBytes[num] = gsMacTxStatus[num].TxBytes;
PreRxBytes[num] = gsMacRxStatus[num].RxBytes;
PreTicks[num] = ticks;
}
t_sec = ticks / 100;
t_min = t_sec / 60;
t_sec %= 60;
t_hr = t_min / 60;
t_min %= 60;
// UART_printf("\n\n");
UART_printf(" RUNNING TIME - %2d : %2d : %2d\n", t_hr, t_min, t_sec);
for (num = 0; num<2; num++)
{
UART_printf("MAC %d ------------------------------------------------------------------------\n", num);
UART_printf("[1] Throughput| Tx:%6d Kbps Rx:%6d Kbps\n", TxRate[num], RxRate[num]);
UART_printf("[2] PKT Count | Tx:%d Rx:%d\n", gsMacTxStatus[num].TXCP, gsMacRxStatus[num].RXGD);
UART_printf("[3] ERR Pkts | Tx:%d Rx:%d\n", gTxErrPacketCnt[num], gRxErrPacketCnt[num]);
UART_printf("[4] TX Status | DEF:%d, EDEF:%d, NCS:%d, ABT:%d, LC:%d\n", gsMacTxStatus[num].DEF, gsMacTxStatus[num].EXDEF, gsMacTxStatus[num].NCS, gsMacTxStatus[num].TXABT, gsMacTxStatus[num].LC);
UART_printf(" | HA:%d, PAU:%d, SQE:%d, BErr:%d, TDU:%d, EMP:%d\n", gsMacTxStatus[num].TXHA, gsMacTxStatus[num].PAU, gsMacTxStatus[num].SQE, gsMacTxStatus[num].TxBErr, gsMacTxStatus[num].TDU, gsMacTxStatus[num].EMP);
UART_printf("[5] RX Status | RP:%d, ALI:%d, PTL:%d, CRCE:%d, CFR:%d, BErr:%d, RXOV:%d\n", gsMacRxStatus[num].RP, gsMacRxStatus[num].ALIE, gsMacRxStatus[num].PTLE,
gsMacRxStatus[num].CRCE, gsMacRxStatus[num].CFR, gsMacRxStatus[num].RxBErr, gsMacRxStatus[num].RXOV);
if (num != EXTERNAL_LOOPBACK_PORT)
UART_printf("\n\n");
else
{
UART_printf("[6] Tx SEQ | Cur=%d, Want=%d, SeqErr=%d, DoChk=%d\n", TxPktSeq, TxPktSeqWanted, TxPktSeqErr, DoChk);
UART_printf("[7] Rx SEQ | Cur=%d, Want=%d, SeqErr=%d\n", RxPktSeq, RxPktSeqWanted, RxPktSeqErr);
}
UART_printf("\n");
}
UART_printf("%c[21A", 0x1B);
}
// Read Error Status and Time
void ReadErrReport(int num)
{
UART_printf("< Error Report >\n") ;
UART_printf("MAC Tx Err Count (Good:%d)\n",(int)gsMacTxStatus[num].TXCP) ;
UART_printf("TXABT: %d, DEF: %d, PAU: %d,\n", (int)gsMacTxStatus[num].TXABT,
(int)gsMacTxStatus[num].DEF, (int)gsMacTxStatus[num].PAU);
UART_printf("EXDEF: %d, NCS: %d, SQE: %d,\n", (int)gsMacTxStatus[num].EXDEF,
(int)gsMacTxStatus[num].NCS, (int)gsMacTxStatus[num].SQE);
UART_printf("LC: %d, TXHA: %d\n",
(int)gsMacTxStatus[num].LC,(int)gsMacTxStatus[num].TXHA);
UART_printf("MAC Rx Err Count (Good:%d)\n",(int)gsMacRxStatus[num].RXGD) ;
UART_printf("ALIE: %d, CRCE: %d,\n",
(int)gsMacRxStatus[num].ALIE, (int)gsMacRxStatus[num].CRCE);
UART_printf("PTLE: %d, RP: %d\n",
(int)gsMacRxStatus[num].PTLE, (int)gsMacRxStatus[num].RP);
if (num==0)
UART_printf("Missed Error Count : %d\n",MPCNT_0) ;
else if (num==1)
UART_printf("Missed Error Count : %d\n",MPCNT_1) ;
}
// Clear Error Report Area
void ClearErrReport(int num)
{
gsMacTxStatus[num].DEF=gsMacTxStatus[num].TXCP=gsMacTxStatus[num].EXDEF=0;
gsMacTxStatus[num].NCS=gsMacTxStatus[num].TXABT=gsMacTxStatus[num].LC=0;
gsMacTxStatus[num].TXHA=gsMacTxStatus[num].PAU=gsMacTxStatus[num].SQE=0;
gsMacTxStatus[num].TxBErr = 0; //CMN [2002/11/01]
gsMacTxStatus[num].TxBytes = 0;
gsMacTxStatus[num].TDU = 0;
gsMacTxStatus[num].EMP = 0;
gsMacRxStatus[num].RP=gsMacRxStatus[num].ALIE=gsMacRxStatus[num].RXGD=0;
gsMacRxStatus[num].PTLE=gsMacRxStatus[num].CRCE=gsMacRxStatus[num].CFR=0;
gsMacRxStatus[num].RxBErr = 0; //CMN [2002/11/01]
gsMacRxStatus[num].RxBytes = 0;
gsMacRxStatus[num].RXOV = 0;
#ifdef USE_TIME
PreTicks[num] = 0;
PreTxBytes[num] = PreRxBytes[num] = 0;
#endif
}
// LAN Initialize Setting
void LanInitialize(int num)
{
ClearErrReport(num);
gErrorPacketCnt[num] = 0;
gTxErrPacketCnt[num] = gRxErrPacketCnt[num] = 0; //CMN
MacRxDoneFlagForLoopBackCheck[num] = 0;
MacTxDoneFlagForLoopBackCheck[num] = 0;
MyMacSrcAddr[0][0] = 0x00 ;
MyMacSrcAddr[0][1] = 0x50 ;
MyMacSrcAddr[0][2] = 0xba ;
MyMacSrcAddr[0][3] = 0x33 ;
MyMacSrcAddr[0][4] = 0xbe ;
MyMacSrcAddr[0][5] = 0x44 ;
MyMacSrcAddr[1][0] = 0x00 ;
MyMacSrcAddr[1][1] = 0x50 ;
MyMacSrcAddr[1][2] = 0xba ;
MyMacSrcAddr[1][3] = 0x33 ;
MyMacSrcAddr[1][4] = 0xbe ;
MyMacSrcAddr[1][5] = 0x55 ;
// Initialize MAC controller
MacInitialize(num) ;
ResetPhyChip(num) ;
// Set MAC address to CAM
SetMacAddr(num) ;
}
// Reset PHY, Auto-Negotiation Enable
void ResetPhyChip(int num)
{
U32 RdValue;
int mode;
if (num == EXTERNAL_LOOPBACK_PORT)
{
MiiStationWrite(num, PHY_CNTL_REG, PHYAD, PHY_FULLDUPLEX | DR_100MB);
}
else
{
#ifdef PHY_Auto_Negotiation
/*
switch(mode)
{
case MODE_DR100_FULL:
MiiStationWrite(num,PHY_ANA_REG,PHYAD,DR100_TX_FULL|IEEE_802_3_CSMA_CD);
break;
case MODE_DR100_HALF:
MiiStationWrite(num,PHY_ANA_REG,PHYAD,DR100_TX_HALF|IEEE_802_3_CSMA_CD);
break;
case MODE_DR10_FULL:
MiiStationWrite(num,PHY_ANA_REG,PHYAD,DR10_TX_FULL|IEEE_802_3_CSMA_CD);
break;
case MODE_DR10_HALF:
MiiStationWrite(num,PHY_ANA_REG,PHYAD,DR10_TX_HALF|IEEE_802_3_CSMA_CD);
break;
default:
break;
}
*/
MiiStationWrite(num, PHY_ANA_REG, PHYAD, DR10_TX_HALF|DR10_TX_FULL|DR100_TX_HALF|
DR100_TX_FULL|IEEE_802_3_CSMA_CD);
MiiStationWrite(num, PHY_CNTL_REG, PHYAD, ENABLE_AN | RESTART_AN);
while (1) // wait for auto-negotiation complete
{
RdValue = MiiStationRead(num, PHY_STATUS_REG, PHYAD) ;
if ((RdValue&AN_COMPLETE)!=0)
break;
}
#else
mode=MODE_DR10_FULL;
switch(mode)
{
case MODE_DR100_FULL:
MiiStationWrite(num, PHY_CNTL_REG, PHYAD, PHY_FULLDUPLEX | DR_100MB);
break;
case MODE_DR100_HALF:
MiiStationWrite(num, PHY_CNTL_REG, PHYAD, DR_100MB);
break;
case MODE_DR10_FULL:
MiiStationWrite(num, PHY_CNTL_REG, PHYAD, PHY_FULLDUPLEX);
break;
case MODE_DR10_HALF:
MiiStationWrite(num, PHY_CNTL_REG, PHYAD, 0);
break;
default:
MiiStationWrite(num, PHY_CNTL_REG, PHYAD, 0);
}
#endif
}
UART_printf("W90N740 MAC%d: ",num);
RdValue = MiiStationRead(num, PHY_CNTL_REG, PHYAD) ;
if ((RdValue&DR_100MB)!=0) // 100MB
{
UART_printf("100MB - ");
if (num==1)
MCMDR_1 |= MCMDR_OPMOD;
else
MCMDR_0 |= MCMDR_OPMOD;
}
else
{
UART_printf("10MB - ");
if (num==1)
MCMDR_1 &= ~MCMDR_OPMOD;
else
MCMDR_0 &= ~MCMDR_OPMOD;
}
if ((RdValue&PHY_FULLDUPLEX)!=0) // Full Duplex
{
UART_printf("Full Duplex\n");
if (num==1)
MCMDR_1 |= MCMDR_FDUP;
else
MCMDR_0 |= MCMDR_FDUP;
}
else
{
UART_printf("Half Duplex\n");
if (num==1)
MCMDR_1 &= ~MCMDR_FDUP;
else
MCMDR_0 &= ~MCMDR_FDUP;
}
}
// MII Interface Station Management Register Write
void MiiStationWrite(int num, U32 PhyInAddr, U32 PhyAddr, U32 PhyWrData)
{
int i=1000;
if (num==0)
{
MIID_0 = PhyWrData ;
MIIDA_0 = PhyInAddr | PhyAddr | PHYBUSY | PHYWR | MDCCR;
while(i--) ;
while( (MIIDA_0 & PHYBUSY) ) ;
}
else if (num==1)
{
MIID_1 = PhyWrData ;
MIIDA_1 = PhyInAddr | PhyAddr | PHYBUSY | PHYWR | MDCCR;
while(i--) ;
while( (MIIDA_1 & PHYBUSY) ) ;
}
}
// MII Interface Station Management Register Read
U32 MiiStationRead(int num, U32 PhyInAddr, U32 PhyAddr)
{
U32 PhyRdData ;
if (num==0)
{
MIIDA_0 = PhyInAddr | PhyAddr | PHYBUSY | MDCCR;
while( (MIIDA_0 & PHYBUSY) ) ;
PhyRdData = MIID_0 ;
}
else if (num==1)
{
MIIDA_1 = PhyInAddr | PhyAddr | PHYBUSY | MDCCR;
while( (MIIDA_1 & PHYBUSY) ) ;
PhyRdData = MIID_1 ;
}
return PhyRdData ;
}
// Set MAC Address to CAM
void SetMacAddr(int num)
{
int i;
//UART_printf("SetMacAddr()\n");
if (num==0)
{
/* Copy MAC Address to global variable */
for (i=0;i<(int)MAC_ADDR_SIZE-2;i++)
gCam0M_0 = (gCam0M_0 << 8) | MyMacSrcAddr[0][i] ;
for (i=(int)(MAC_ADDR_SIZE-2);i<(int)MAC_ADDR_SIZE;i++)
gCam0L_0 = (gCam0L_0 << 8) | MyMacSrcAddr[0][i] ;
gCam0L_0 = (gCam0L_0 << 16) ;
FillCamEntry(0, 0, gCam0M_0, gCam0L_0);
}
else if (num==1)
{
/* Copy MAC Address to global variable */
for (i=0;i<(int)MAC_ADDR_SIZE-2;i++)
gCam0M_1 = (gCam0M_1 << 8) | MyMacSrcAddr[1][i] ;
for (i=(int)(MAC_ADDR_SIZE-2);i<(int)MAC_ADDR_SIZE;i++)
gCam0L_1 = (gCam0L_1 << 8) | MyMacSrcAddr[1][i] ;
gCam0L_1 = (gCam0L_1 << 16) ;
FillCamEntry(1, 0, gCam0M_1, gCam0L_1);
}
}
void EnableCamEntry(int num, int entry)
{
if (num==0)
CAMEN_0 |= 0x00000001<<entry ;
else if (num==1)
CAMEN_1 |= 0x00000001<<entry ;
}
void DisableCamEntry(int num, int entry)
{
if (num==0)
CAMEN_0 &= ~(0x00000001<<entry) ;
else if (num==1)
CAMEN_1 &= ~(0x00000001<<entry) ;
}
void FillCamEntry(int num, int entry, U32 msw, U32 lsw)
{
if (num==0)
{
CAMxM_Reg_0(entry) = msw;
CAMxL_Reg_0(entry) = lsw;
}
else if (num==1)
{
CAMxM_Reg_1(entry) = msw;
CAMxL_Reg_1(entry) = lsw;
}
EnableCamEntry(num,entry);
}
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