clk_rst.v

时钟和复位模块的仿真程序设计

//----------------------------------------------------------------------------
// 
//  Name:  clk_rst.v   
// 
//  Description: Clock/reset moduel for I2C serial controller simulation
// 
//  $Revision: 1.0 $          
//  
//  Copyright 2004 Lattice Semiconductor Corporation.  All rights reserved.
//
//----------------------------------------------------------------------------
// Permission:
//
//   Lattice Semiconductor grants permission to use this code for use
//   in synthesis for any Lattice programmable logic product.  Other
//   use of this code, including the selling or duplication of any
//   portion is strictly prohibited.
//
// Disclaimer:
//
//   This VHDL or Verilog source code is intended as a design reference
//   which illustrates how these types of functions can be implemented.
//   It is the user's responsibility to verify their design for
//   consistency and functionality through the use of formal
//   verification methods.  Lattice Semiconductor provides no warranty
//   regarding the use or functionality of this code.
//----------------------------------------------------------------------------
//
//    Lattice Semiconductor Corporation
//    5555 NE Moore Court
//    Hillsboro, OR 97124
//    U.S.A
//
//    TEL: 1-800-Lattice (USA and Canada)
//    408-826-6000 (other locations)
//
//    web: http://www.latticesemi.com/
//    email: [e-mail]
// 
//----------------------------------------------------------------------------

`timescale 1 ns /  100 ps

/*
This is a generic clock/reset module.  It takes into account the reset 
recovery time for Vantis Macrocell flip-flops.
*/

module clk_rst( clk,
                rst_l);

//-------------------------------------------------------------------
// port list

output          clk;
output          rst_l;

//-------------------------------------------------------------------
// registers

wire            clk;
reg             clk_en;
reg             int_clk;
reg             rst_l;

//-------------------------------------------------------------------
// clock generator

// clock parameter frequencies

parameter clk_16 = 60;              // 16.6 MHz
parameter clk_20 = 40;              // 20.0 MHz
parameter clk_33 = 30;              // 33.0 MHz
parameter clk_50 = 20;              // 50.0 MHz
parameter clk_62 = 16;              // 62.5 MHz
parameter clk_71 = 14;              // 71.4 MHz
parameter clk_83 = 12;              // 83.3 MHz
parameter clk_10 = 10;              // 100  MHz
parameter clk_12 = 8;               // 125  MHz

parameter period = clk_50;          // using 50 MHz

initial 
    int_clk  <= 1'b0;               // internal clock reset

always #(period/2) int_clk = ~int_clk;

//-------------------------------------------------------------------
// reset generator

// reset parameters

parameter reset_recovery = 15;      // 15 nsec between res and clk
parameter reset_time = 500;         // make reset time whatever  


initial begin
    
    clk_en   <= 1'b0;               // turn off clock to outside world
    rst_l    <= 1'b0;               // turn on reset signal
    #reset_time;                    // wait for reset time       
    @(posedge int_clk);             // at rising edge of clock
    rst_l    <= 1'b1;               // turn off reset
    #reset_recovery;                // wait for recovery time
    @(negedge int_clk);             // at trailing edge of clock
    clk_en   <= 1'b1;               // enable clock
    
    $display($time,": Simulation Starting");
    $display();
    end             

//-------------------------------------------------------------------
// clock enable

assign clk = int_clk & clk_en;

                
endmodule                                    

//------------------------------- E O F --------------------------------------